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參數(shù)資料
| 型號(hào)： | EVAL-AD7765EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/33頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD7765 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 156k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | ±3.2768 V |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 300mW @ 156kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7765 |
| 已供物品： | 板 |
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AD7765
Rev. A | Page 23 of 32
DAISY CHAINING
Daisy chaining allows numerous devices to use the same digital
interface lines. This feature is especially useful for reducing
component count and wiring connections, such as in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register. When daisy chaining is used, all devices in the
chain must operate in a common power mode and at a common
decimation rate.
The block diagram in Figure 39 shows how to connect devices
to achieve daisy-chain functionality. Figure 39 shows four
AD7765 devices daisy-chained together with a common MCLK
signal applied.
READING DATA IN DAISY-CHAIN MODE
Referring to Figure 39, note that the SDO line of AD7765 (A)
provides the output data from the chain of AD7765 converters.
Also, note that for the last device in the chain, AD7765 (D), the
SDI pin is connected to ground. All of the devices in the chain
must use common MCLK and SYNC
To enable the daisy-chain conversion process, apply a common
signals.
SYNC
After a
pulse to all devices (see the Synchronization section).
SYNC pulse is applied to all devices, the filter settling
time must pass before the FILTER-SETTLE bit is asserted
indicating valid conversion data at the output of the chain of
devices. As shown in Figure 40, the first conversion result is
output from the device labeled AD7765 (A). This 32-bit
conversion result is then followed by the conversion results
from the devices AD7765 (B), AD7765 (C), and AD7765 (D),
with all conversion results output in an MSB-first sequence. The
signals output from the daisy chain are the stream of conversion
results from the SDO pin of AD7765 (A) and the FSO
The falling edge of
signal
output by the first device in the chain, AD7765 (A).
FSO signals the MSB of the first conversion
output in the chain.
The maximum number of devices that can be daisy-chained is
dependent on the decimation rate selected. Calculate the
maximum number of devices that can be daisy-chained by
simply dividing the chosen decimation rate by 32 (the number
of bits that must be clocked out for each conversion).
FSO stays logic low throughout the 32 SCO
clock periods needed to output the AD7765 (A) result and then
goes logic high during the output of the conversion results from
the AD7765 (B), AD7765 (C), and AD7765 (D) devices.
provides the maximum number of chained devices for each
decimation rate.
Table 12. Maximum Chain Length for All Decimation Rates
Decimation Rate
Maximum Chain Length
256×
8
128×
4
SYNC
SDI
FSI
SDO
MCLK
AD7765
(D)
FSI
SYNC
MCLK
SYNC
SDI
FSI
SDO
MCLK
AD7765
(C)
SYNC
SDI
FSI
SDO
MCLK
AD7765
(B)
SYNC
SDI
FSI
MCLK
AD7765
(A)
SDO
FSO
06519-
018
Figure 39. Daisy Chaining Four Devices in Decimate 128× Mode Using a 40 MHz MCLK Signal
SCO
FSO (A)
32 ×
tSCO
32 ×
tSCO
32 ×
tSCO
32 ×
tSCO
SDO (A)
AD7765 (A)
32-BIT OUTPUT
AD7765 (B)
32-BIT OUTPUT
AD7765 (C)
32-BIT OUTPUT
AD7765 (D)
32-BIT OUTPUT
AD7765 (A)
32-BIT OUTPUT
AD7765 (B)
32-BIT OUTPUT
SDI (A) = SDO (B)
AD7765 (B)
AD7765 (C)
AD7765 (D)
AD7765 (B)
AD7765 (C)
SDI (B) = SDO (C)
AD7765 (C)
AD7765 (D)
AD7765 (C)
AD7765 (D)
SDI (C) = SDO (D)
AD7765 (D)
06519-
019
Figure 40. Daisy-Chain Mode, Data Read Timing Diagram
(for the Daisy-Chain Configuration Shown in Figure 39)
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