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| 型號： | EVAL-AD7879EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7879 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，觸摸屏控制器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD7879 |
| 主要屬性： | 4 線電阻式觸控屏控制器，I²C 和 SPI 接口 |
| 次要屬性： | 圖形用戶界面，USB 接口 |
| 已供物品： | 板，線纜，CD，觸控屏 |
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AD7879/AD7889
Rev. C | Page 23 of 40
Table 13. Control Register 2
Address
Bit Name
Data Bit
Description
Default
Value
0x02
PM[1:0]
[15:14]
ADC power management.
0x4040
00 = full shutdown; the ADC, oscillator, bias, and temperature sensor are all powered down.
01 = analog blocks to be powered down depend on the ADC mode.
If ADC mode is master mode, the ADC, oscillator, bias, and temperature sensor are powered
down and must wake up when the user touches the screen.
If ADC mode is slave mode, the ADC and temperature sensor are powered down when not
being used. They wake up automatically when required. The oscillator and bias are powered
up because they are needed to measure time. This also applies to the single-conversion mode.
10 = ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode.
11 = same as 01.
GPIO EN
13
GPIO enable.
0 = AUX/VBAT channel active.
1 = GPIO enabled on AUX/VBAT/GPIO pin.
GPIO DAT
12
GPIO data bit.
GPIO DIR
11
GPIO direction.
0 = output.
1 = input.
GPIO POL
10
GPIO polarity.
0 = GPIO pin is active low.
1 = GPIO pin is active high.
SER/DFR
9
Selects normal (single-ended) or ratiometric (differential) conversion.
0 = ratiometric (differential).
1 = normal (single-ended).
AVG[1:0]
[8:7]
ADC averaging.
00 = 2 middle values averaged (one measurement when median filter is disabled).
01 = 4 middle values averaged.
10 = 8 middle values averaged.
11 = 16 values averaged.
MED[1:0]
[6:5]
Median filter size.
00 = median filter disabled.
01 = 4 measurements.
10 = 8 measurements.
11 = 16 measurements.
SW/RST
4
Software reset; digital logic is reset when this bit is set.
FCD[3:0]
[3:0]
ADC first conversion delay.1
Starts at 128 s (default) and continues to 4.096 ms in steps of 128 s (see Table 22).
1
This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow for screen settling and before the first conversion to allow the
ADC to power up.
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