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參數(shù)資料
| 型號(hào)： | EVAL-AD9838SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9838 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9838 |
| 主要屬性： | USB 供電或外部電源 |
| 次要屬性： | SPI 接口 |
| 已供物品： | 板，線纜，CD，文檔 |
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AD9838
Rev. A | Page 20 of 32
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered; with fine tuning, only the 14 LSBs are altered. By
setting the B28 control bit (Bit D13) to 0, the 28-bit frequency
register operates as two 14-bit registers, one containing the
14 MSBs and the other containing the 14 LSBs. In this way, the
14 MSBs of the frequency word can be altered independently
of the 14 LSBs, and vice versa. The HLB bit (Bit D12) in the
control register identifies which 14 bits are being altered (see
Table 13. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register
SDATA Input
Result of Input Word
0000 0000 0000 0000
Control word write
(D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 0, that is, LSBs
1011 1111 1111 1111
FREQ1 register write
(D15, D14 = 10), 14 LSBs = 0x3FFF
Table 14. Writing 0x00FF to the 14 MSBs of the FREQ0 Register
SDATA Input
Result of Input Word
0001 0000 0000 0000
Control word write
(D15, D14 = 00), B28 (D13) = 0,
HLB (D12) = 1, that is, MSBs
0100 0000 1111 1111
FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x00FF
Writing to a Phase Register
When writing to a phase register, Bit D15 and Bit D14 are set
to 11. Bit D13 identifies the phase register that is being loaded.
Table 15. Phase Register Bits
D15
D14
D13
D12
D11 to D0
1
0
X
12 PHASE0 register bits
1
X
12 PHASE1 register bits
RESET FUNCTION
The reset function resets the appropriate internal registers to 0
to provide an analog output of midscale. A reset does not reset
the phase, frequency, or control registers. When the AD9838 is
powered up, the part should be reset (see the Powering Up the
AD9838 section). To reset the AD9838, set the RESET pin or bit
to 1. To take the part out of reset, set the RESET pin or bit to 0.
A signal appears at the DAC output eight or nine MCLK cycles
after the RESET pin or bit is set to 0.
The reset function is controlled by either the RESET pin or the
RESET control bit. If the PIN/SW control bit = 0, the RESET bit
controls the function; if the PIN/SW control bit = 1, the RESET
pin controls the function (see Table 16).
Table 16. Applying the Reset Function
RESET Pin
RESET Bit
PIN/SW Bit
Result
0
X
1
No reset applied
1
X
1
Internal registers reset
X
0
No reset applied
X
1
0
Internal registers reset
The effect of asserting the RESET pin is immediately evident
at the output—that is, the 0-to-1 transition of this pin is not
sampled. However, the negative (1-to-0) transition of the
RESET pin is sampled on the internal falling edge of MCLK.
SLEEP FUNCTION
Sections of the AD9838 that are not in use can be powered
down to minimize power consumption by using the sleep
function. The parts of the chip that can be powered down are
the internal clock and the DAC. The DAC can be powered
down using hardware or software (see Table 17).
Table 17. Applying the Sleep Function
SLEEP
Pin
SLEEP1
Bit
SLEEP12
Bit
PIN/SW
Bit
Result
0
X
1
No power-down
1
X
1
DAC powered down
X
0
No power-down
X
0
1
0
DAC powered down
X
1
0
Internal clock disabled
X
1
0
DAC powered down and
internal clock disabled
DAC Powered Down
When the AD9838 is used to output the MSB of the DAC data
only, the DAC is not required. The DAC can be powered down
to reduce power consumption.
Internal Clock Disabled
When the internal clock of the AD9838 is disabled, the DAC
output remains at its present value because the NCO is no longer
accumulating. New frequency, phase, and control words can be
written to the part when the SLEEP1 control bit is active. Because
the synchronizing clock (FSYNC) remains active, the selected
frequency and phase registers can also be changed either at the
pins or by using the control bits. Setting the SLEEP1 bit to 0
enables the MCLK. Any changes made to the registers while
SLEEP1 was active are observed at the output after a latency
period (see the Latency Period section).
The effect of asserting the SLEEP pin is immediately evident
at the output—that is, the 0-to-1 transition of this pin is not
sampled. However, the negative (1-to-0) transition of the SLEEP
pin is sampled on the internal falling edge of MCLK.
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