參數(shù)資料
型號(hào)： EVAL-AD9838SDZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9838
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9838
主要屬性： USB 供電或外部電源
次要屬性： SPI 接口
已供物品： 板，線纜，CD，文檔
AD9838
Rev. A | Page 25 of 32
AD9838 to 68HC11/68L11 Interface
Figure 28 shows the serial interface between the AD9838 and
the 68HC11/68L11 microcontroller. The microcontroller is con-
figured as the master by setting the MSTR bit in the SPCR to 1.
This setting provides a serial clock on SCK; the MOSI output
drives the serial data line, SDATA. Because the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for correct
operation of the interface are as follows:
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
When data is to be transmitted to the AD9838, the FSYNC line
(PC7) is taken low. Serial data from the 68HC11/68L11 is trans-
mitted in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. Data is transmitted MSB first. To load data
into the AD9838, PC7 is held low after the first eight bits are
transferred, and a second serial write operation is performed to
the AD9838. Only after the second eight bits are transferred
should FSYNC be taken high again.
AD9838
FSYNC
SDATA
SCLK
68HC11/68L11
PC7
MOSI
SCK
090
77
-03
3
Figure 28. 68HC11/68L11 to AD9838 Interface
AD9838 to 80C51/80L51 Interface
Figure 29 shows the serial interface between the AD9838 and
the 80C51/80L51 microcontroller. The microcontroller is oper-
ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of
the AD9838, and RxD drives the serial data line, SDATA. The
FSYNC signal is derived from a bit programmable pin on the
port (P3.3 is shown in Figure 29).
When data is to be transmitted to the AD9838, P3.3 is taken low.
The 80C51/80L51 transmits data in 8-bit bytes with only eight
falling SCLK edges occurring in each cycle. To load the remain-
ing eight bits to the AD9838, P3.3 is held low after the first eight
bits are transmitted, and a second write operation is initiated to
transmit the second byte of data. P3.3 is taken high following
the completion of the second write operation. SCLK should idle
high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has the
LSB first. The AD9838 accepts the MSB first (the four MSBs are
the control information, the next four bits are the address, and
the eight LSBs contain the data when writing to a destination
register). Therefore, the transmit routine of the 80C51/80L51
must take this into account and rearrange the bits so that the
MSB is output first.
AD9838
FSYNC
SDATA
SCLK
80C51/80L51
P3.3
RXD
TXD
0
90
77
-0
34
Figure 29. 80C51/80L51 to AD9838 Interface
AD9838 to DSP56002 Interface
Figure 30 shows the interface between the AD9838 and the
DSP56002. The DSP56002 is configured for normal mode asyn-
chronous operation with a gated internal clock (SYN = 0, GCK = 1,
SCKD = 1). The frame sync pin is generated internally (SC2 = 1),
the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame
sync signal frames the 16 bits (FSL = 0). The frame sync signal is
available on the SC2 pin, but it must be inverted before it is applied
to the AD9838. The interface to the DSP56000/DSP56001 is
similar to that of the DSP56002.
AD9838
FSYNC
SDATA
SCLK
DSP56002
SC2
STD
SCK
09
07
7-
0
35
Figure 30. DSP56002 to AD9838 Interface
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