參數(shù)資料
型號(hào): EVAL-AD9838SDZ
廠商: Analog Devices Inc
文件頁數(shù): 28/32頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9838
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),直接數(shù)字合成(DDS)
嵌入式:
已用 IC / 零件: AD9838
主要屬性: USB 供電或外部電源
次要屬性: SPI 接口
已供物品: 板,線纜,CD,文檔
AD9838
Rev. A | Page 5 of 32
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter1
Limit at TMIN to TMAX
Unit
Description
t1
200/62.5
ns min
MCLK period (5 MHz/16 MHz)
t2
80/26
ns min
MCLK high duration (5 MHz/16 MHz)
t3
80/26
ns min
MCLK low duration (5 MHz/16 MHz)
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high duration
t6
10
ns min
SCLK low duration
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8
10
ns min
SCLK falling edge to FSYNC rising edge time
t4 5
ns max
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
8
ns min
FSELECT, PSELECT setup time before MCLK rising edge
t11A
8
ns min
FSELECT, PSELECT setup time after MCLK rising edge
t12
5
ns min
SCLK high to FSYNC falling edge setup time
1 Guaranteed by design; not production tested.
Timing Diagrams
MCLK
t1
t3
t2
09
07
7
-00
3
Figure 2. Master Clock
FSELECT,
PSELECT
VALID DATA
MCLK
t11A
t11
09
07
7-
0
04
Figure 3. Control Timing
D0
SCLK
FSYNC
SDATA
D15
D14
D2
D1
D15
D14
t12
t7
t6
t8
t5
t4
t9
t10
09
07
7-
0
05
Figure 4. Serial Timing
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