參數資料
型號: EVAL-ADAU1966Z
廠商: Analog Devices Inc
文件頁數: 18/52頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADAU1966
標準包裝: 1
DAC 的數量: 16
位數: 24
采樣率(每秒): 192k
數據接口: I²S,串行,SPI?
DAC 型: 電壓
工作溫度: -40°C ~ 105°C
已供物品:
已用 IC / 零件: ADAU1966
Data Sheet
ADAU1966
Rev. D | Page 25 of 52
REGISTER DETAILS
PLL AND CLOCK CONTROL 0 REGISTER
Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0
Table 24. Bit Descriptions for PLL_CLK_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
PLLIN
PLL Input Select. Selects between MCLKI/XTALI or DLRCLK as the input to
the PLL.
0x0
RW
00
MCLKI or XTALI
01
DLRCLK
10
Reserved
11
Reserved
[5:4]
XTAL_SET
XTAL Oscillator Setting. XTALO pin status.
0x0
RW
00
XTAL Oscillator Enabled
01
Reserved
10
Reserved
11
XTALO Off
3
SOFT_RST
Software Reset Control. This bit resets all circuitry inside the IC, except
I2C/SPI communications. All control registers are reset to default values,
except Register 0x00 and Register 0x01. The PLL_CLK_CTRLx registers do
not change state.
0x0
RW
0
Normal Operation
1
Device in Reset
[2:1]
MCS
Master Clock Select. MCLKI/XTALI pin functionality (PLL active), master
clock rate setting. The following values are for the fS rate window from
32 kHz to 48 kHz. See Table 12 for details when using other fS selections.
0x0
RW
00
256 × fS MCLK (44.1 kHz or 48 kHz)
01
384 × fS MCLK (44.1 kHz or 48 kHz)
10
512 × fS MCLK (44.1 kHz or 48 kHz)
11
768 × fS MCLK (44.1 kHz or 48 kHz)
0
PUP
Master Power-Up Control. This bit must be set to 1 as the first register
write to power up the IC.
0x0
RW
0
Master Power-Down
1
Master Power-Up
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