參數(shù)資料
型號: EVAL-ADAV803EBZ
廠商: Analog Devices Inc
文件頁數(shù): 47/60頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADAV803
標準包裝: 1
主要目的: 接口,模擬前端(AFE)
已用 IC / 零件: ADAV803
已供物品:
相關(guān)產(chǎn)品: ADAV803ASTZ-ND - IC CODEC AUDIO R-DVD 3.3V 64LQFP
ADAV803ASTZ-REEL-ND - IC CODEC AUDIO R-DVD 3.3V 64LQFP
ADAV803
Rev. A | Page 51 of 60
ADC Control Register 1—Address 1101110 (0x6E)
Table 116. ADC Control Register 1 Bit Map
7
6
5
4
3
2
1
0
AMC
HPF
PWRDWN
ANA_PD
MUTER
MUTEL
PLPD
PRPD
Table 117. ADC Control Register 1 Bit Descriptions
Bit Name
Description
AMC
ADC modulator clock.
0 = ADC MCLK/2 (128 × fS).
1 = ADC MCLK/4 (64 × fS).
HPF
High-pass filter enable.
0 = Normal.
1 = HPF enabled.
PWRDWN
ADC power-down.
0 = Normal.
1 = Power-down.
ANA_PD
ADC analog section power-down.
0 = Normal.
1 = Power-down.
MUTER
Mute ADC right channel.
0 = Normal.
1 = Muted.
MUTEL
Mute ADC left channel.
0 = Normal.
1 = Muted.
PLPD
PGA left power-down.
0 = Normal.
1 = Power-down.
PRPD
PGA right power-down.
0 = Normal.
1 = Power-down.
ADC Control Register 2—Address 1101111 (0x6F)
Table 118. ADC Control Register 2 Bit Map
7
6
5
4
3
2
1
0
Reserved
BUF_PD
Reserved
MCD1
MCD0
Table 119. ADC Control Register 2 Bit Descriptions
Bit Name
Description
BUF_PD
Reference buffer power-down control.
0 = Normal.
1 = Power-down.
MCD[1:0]
ADC master clock divider.
00 = Divide by 1.
01 = Divide by 2.
10 = Divide by 3.
11 = Divide by 1.
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