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| 型號： | EVAL-ADCMP609BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADCMP609 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 比較器，單路 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADCMP609 |
| 主要屬性： | CMOS 和 TTL 兼容輸出 |
| 次要屬性： | 關(guān)機引腳 |
| 已供物品： | 板 |
Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V,
Single-Supply TTL/CMOS Comparator
ADCMP609
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2007–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Fully specified rail-to-rail at VCC = 2.5 V to 5.5 V
Input common-mode voltage from 0.2 V to VCC + 0.2 V
Low glitch TTL-/CMOS-compatible output stage
40 ns propagation delay
Low power 1 mW at 2.5 V
Shutdown pin
Programmable hysteresis
Power supply rejection > 60 dB
40°C to +125°C operation
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
FUNCTIONAL BLOCK DIAGRAM
06
91
8-
0
01
ADCMP609
NONINVERTING
INPUT
INVERTING
INPUT
Q OUTPUT
+
–
SDN
Figure 1.
GENERAL DESCRIPTION
The ADCMP609 is a fast comparator fabricated on XFCB2, an
Analog Devices, Inc., proprietary process. These comparators
are exceptionally versatile and easy to use. Features include an
input range from VEE 0.2 V to VCC + 0.2 V, low noise, TTL-
/CMOS-compatible output drivers, and adjustable hysteresis
and/or shutdown inputs.
The device offers 40 ns propagation delay driving a 15 pF load
with 10 mV overdrive on 500 μA typical supply current.
A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a 0.2 V to +3.0 V
input signal range up to a +5.5 V positive supply with a 0.2 V
to +5.7 V input signal range.
The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specifications and to degrade
in a graceful and linear fashion as additional capacitance is added.
The input stage of the comparator offers robust protection against
large input overdrive, and the outputs do not phase reverse when
the valid input signal range is exceeded. A programmable hysteresis
feature is also provided.
The ADCMP609, available in an 8-lead MSOP package, features
a shutdown pin and hysteresis control.
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