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| 型號： | EVAL-ADUC834QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC834 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC834 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
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REV. A
ADuC834
–43–
PSMCON
Power Supply Monitor Control Register
SFR Address
DFH
Power-On Default Value
DEH
Bit Addressable
No
POWER SUPPLY MONITOR
As its name suggests, the Power Supply Monitor, once enabled,
monitors both supplies (AVDD or DVDD) on the ADuC834. It will
indicate when any of the supply pins drop below one of four
user-selectable voltage trip points from 2.63 V to 4.63 V. For
correct operation of the Power Supply Monitor function, AVDD
must be equal to or greater than 2.7 V. Monitor function is
controlled via the PSMCON SFR. If enabled via the IEIP2 SFR,
the monitor will interrupt the core using the PSMI bit in the
PSMCON SFR. This bit will not be cleared until the failing power
supply has returned above the trip point for at least 250 ms. This
monitor function allows the user to save working registers to avoid
possible data loss due to the low supply condition, and also
ensures that normal code execution will not resume until a safe
supply level has been well established. The supply monitor is also
protected against spurious glitches triggering the interrupt circuit.
Table XX. PSMCON SFR Bit Designations
Bit
Name
Description
7
CMPD
DVDD Comparator Bit.
This is a read-only bit and directly reflects the state of the DVDD comparator.
Read 1 indicates the DVDD supply is above its selected trip point.
Read 0 indicates the DVDD supply is below its selected trip point.
6CMPA
AVDD Comparator Bit.
This is a read-only bit and directly reflects the state of the AVDD comparator.
Read 1 indicates the AVDD supply is above its selected trip point.
Read 0 indicates the AVDD supply is below its selected trip point.
5
PSMI
Power Supply Monitor Interrupt Bit.
This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low
analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or
CMPA return (and remain) high, a 250 ms counter is started. When this counter timesout, the
PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator
output is low, it is not possible for the user to clear PSMI.
4
TPD1
DVDD Trip Point Selection Bits.
3
TPD0
These bits select the DVDD trip point voltage as follows:
TPD1
TPD0
Selected DVDD Trip Point (V)
00
4.63
01
3.08
10
2.93
11
2.63
2
TPA1
AVDD Trip Point Selection Bits.
1
TPA0
These bits select the AVDD trip point voltage as follows:
TPA1TPA0
Selected AVDD Trip Point (V)
00
4.63
01
3.08
10
2.93
11
2.63
0
PSMEN
Power Supply Monitor Enable Bit.
Set to 1 by the user to enable the Power Supply Monitor Circuit.
Cleared to 0 by the user to disable the Power Supply Monitor Circuit.
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