參數(shù)資料
型號: EVAL-ADV7179EBZ
廠商: Analog Devices Inc
文件頁數(shù): 16/52頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADV7179
設(shè)計資源: ADV7174/79 Eval Brd Docs
標準包裝: 1
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: ADV7179
主要屬性: NTSC/PAL 數(shù)字視頻編碼器
次要屬性: I²C 接口
已供物品:
ADV7174/ADV7179
Rev. B | Page 23 of 52
Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A
VSYNC low transition when HSYNC is high indicates the start
of an even field. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7174/ADV7179 automatically
blanks all normally blank lines as per CCIR-624. Mode 2 is
illustrated in
(NTSC) and
(PAL).
illustrates the
HSYNC, BLANK, and VSYNC for an even-to-
odd field transition relative to the pixel data.
illustrates the
HSYNC, BLANK, and VSYNC for an odd-to-
even field transition relative to the pixel data.
HSYNC
VSYNC
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
02980-A
-029
Figure 29. Timing Mode 2 Even-to-Odd Field Transition Master/Slave
VSYNC
PIXEL
DATA
Cb
Y
Cr
Y
Cb
HSYNC
BLANK
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
PAL = 864
× CLOCK/2
NTSC = 858
× CLOCK/2
02980-A
-082
Figure 30. Timing Mode 2 Odd-to-Even Field Transition Master/Slave
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