參數(shù)資料
型號： EVAL-ADV7179EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/52頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADV7179
設(shè)計(jì)資源： ADV7174/79 Eval Brd Docs
標(biāo)準(zhǔn)包裝： 1
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7179
主要屬性： NTSC/PAL 數(shù)字視頻編碼器
次要屬性： I²C 接口
已供物品： 板
ADV7174/ADV7179
Rev. B | Page 17 of 52
COMPOSITE
VIDEO
(e.g., VCR
OR CABLE)
HSYNC
FIELD/VSYNC
CLOCK
GREEN/LUMA/Y
RED/CHROMA/Pr
BLUE/COMPOSITE/Pb
AD7174/ADV7179
P7–P0
SCRESET/RTC
VIDEO
DECODER
(e.g., ADV7183A)
H/LTRANSITION
COUNT START
4 BITS
RESERVED
5 BITS
RESERVED
RESET
BIT3
SEQUENCE
BIT2
RESERVED
14 BITS
RESERVED
LOW
128
RTC
TIME SLOT: 01
14
67 68
NOT USED IN THE
ADV7174/ADV7179
19
VALID
SAMPLE
INVALID
SAMPLE
FSC PLL INCREMENT1
8/LLC
21
0
13
NOTES
1FSC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7174/ADV7179 FSC DDS REGISTER IS
FSC PLL INCREMENT BITS 21:0 PLUS BITS 0:9 OF THE SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD
BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7174/ADV7179.
2SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
3RESET BIT
RESET ADV7174/ADV7179 DDS
0
02980-A
-019
Figure 19. RTC Timing and Connections
Vertical Blanking Data Insertion
It is possible to allow encoding of incoming YCbCr data on
those lines of VBI that do not bear line sync or pre-/post-
equalization pulses (see Figure 21 to Figure 32). This mode of
operation is called partial blanking and is selected by setting
MR32 to 1. It allows the insertion of any VBI data (opened VBI)
into the encoded output waveform. This data is present in the
digitized incoming YCbCr data stream, for example. WSS data,
CGMS, VPS, and so on. Alternatively, the entire VBI may be
blanked (no VBI data inserted) on these lines by setting MR32
to 0.
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7174/ADV7179 is controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchro-
nization pattern. A synchronization pattern is sent immediately
before and after each line during active picture and retrace.
Mode 0 is illustrated in Figure 20. The HSYNC, FIELD/VSYNC,
and BLANK (if not used) pins should be tied high during this
mode.
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7174/ADV7179 generates H, V, and F signals required
for the SAV and EAV time codes in the CCIR-656 standard. The
H bit is output on the HSYNC pin, the V bit is output on the
BLANK pin, and the F bit is output on the FIELD/VSYNC pin.
Mode 0 is illustrated in
(NTSC) and
(PAL).
The H, V, and F transitions relative to the video waveform are
illustrated in
.
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