VAA = 2.8 V, V" />
參數(shù)資料
型號(hào): EVAL-ADV7179EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 45/52頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR ADV7179
設(shè)計(jì)資源: ADV7174/79 Eval Brd Docs
標(biāo)準(zhǔn)包裝: 1
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: ADV7179
主要屬性: NTSC/PAL 數(shù)字視頻編碼器
次要屬性: I²C 接口
已供物品:
ADV7174/ADV7179
Rev. B | Page 5 of 52
2.8 V TIMING SPECIFICATIONS
VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX1, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulse Width, t1
0.6
μs
SCLOCK Low Pulse Width, t2
1.3
μs
Hold Time (Start Condition), t3
After this period the first clock is generated
0.6
μs
Setup Time (Start Condition), t4
Relevant for repeated start condition
0.6
μs
Data Setup Time, t5
100
ns
SDATA, SCLOCK Rise Time, t6
300
ns
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
μs
ANALOG OUTPUTS3, 4
Analog Output Delay
7
ns
DAC Analog Output Skew
0
ns
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
3.5
ns
Data Hold Time, t12
4
ns
Control Setup Time, t11
4
ns
Control Hold Time, t12
3
ns
Digital Output Access Time, t13
12
ns
Digital Output Hold Time, t14
8
ns
Pipeline Delay, tPD5
48
Clock Cycles
TELETEXT3, 4, 6
Digital Output Access Time, t16
23
ns
Data Setup Time, t17
2
ns
Data Hold Time, t18
6
ns
RESET Low Time
6
ns
1 Temperature range TMIN to TMAX: –20°C to +85°C.
2 TTL input values are 0 V to 2.8 V, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
3 Guaranteed by characterization.
4 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 Teletext Port consists of the following:
Teletext Output: TTXREQ
Teletext Input: TTX
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