Revision 10 1-7 To exit the LP mode, the LP pin must be driven LOW for over 200 s to allow for the charge pumps to power-up and de" />
參數(shù)資料
型號(hào): EX256-PTQ100I
廠商: Microsemi SoC
文件頁(yè)數(shù): 3/48頁(yè)
文件大?。?/td> 0K
描述: IC FPGA ANTIFUSE 12K 100-TQFP
標(biāo)準(zhǔn)包裝: 90
系列: EX
邏輯元件/單元數(shù): 512
輸入/輸出數(shù): 81
門數(shù): 12000
電源電壓: 2.3 V ~ 2.7 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
eX Family FPGAs
Revision 10
1-7
To exit the LP mode, the LP pin must be driven LOW for over 200 s to allow for the charge pumps to
power-up and device initialization can begin.
Table 1-3 illustrates the standby current of eX devices in LP mode.
Table 1-3 Standby Power of eX Devices in LP Mode Typical Conditions, VCCA, VCCI = 2.5 V,
TJ = 25C
Product
Low Power Standby Current
Units
eX64
100
A
eX128
111
A
eX256
134
A
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