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參數(shù)資料
| 型號(hào)： | EX256-TQ100A |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 46/48頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA ANTIFUSE 12K 100-TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | EX |
| 邏輯元件/單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 81 |
| 門數(shù)： | 12000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
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eX Family FPGAs
Revision 10
1-3
Routing Resources
Clusters and SuperClusters can be connected through the use of two innovative local routing resources
called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of
modules within Clusters and SuperClusters (Figure 1-4). This routing architecture also dramatically
reduces the number of antifuses required to complete a circuit, ensuring the highest possible
performance.
DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring
R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable
interconnection to achieve its fast signal propagation time of less than 0.1 ns (–P speed grade).
FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and
vertical routing with the SuperCluster immediately below it. Only one programmable connection is used
in a FastConnect path, delivering maximum pin-to-pin propagation of 0.3 ns (–P speed grade).
In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented
routing resources known as segmented routing and high-drive routing. The segmented routing structure
of Microsemi provides a variety of track lengths for extremely fast routing between SuperClusters. The
exact combination of track lengths and antifuses within each path is chosen by the fully automatic place-
and-route software to minimize signal propagation delays.
Clock Resources
eX’s high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired
from the HCLK buffer to the clock select MUX in each R-Cell. HCLK cannot be connected to
combinational logic. This provides a fast propagation path for the clock signal, enabling the 3.9 ns clock-
to-out (pad-to-pad) performance of the eX devices. The hard-wired clock is tuned to provide a clock skew
of less than 0.1 ns worst case. If not used, the HCLK pin must be tied LOW or HIGH and must not be left
floating. Figure 1-5 describes the clock circuit used for the constant load HCLK.
HCLK does not function until the fourth clock cycle each time the device is powered up to prevent false
output levels due to any possible slow power-on-reset signal and fast start-up clock circuit. To activate
HCLK from the first cycle, the TRST pin must be reserved in the Design software and the pin must be tied
to GND on the board. (See the "TRST, I/O Boundary Scan Reset Pin" on page 1-32).
The remaining two clocks (CLKA, CLKB) are global routed clock networks that can be sourced from
external pins or from internal logic signals (via the CLKINT routed clock buffer) within the eX device.
CLKA and CLKB may be connected to sequential cells or to combinational logic. If CLKA or CLKB is
sourced from internal logic signals, the external clock pin cannot be used for any other input and must be
tied LOW or HIGH and must not float. Figure 1-6 describes the CLKA and CLKB circuit used in eX
devices.
Figure 1-4 DirectConnect and FastConnect for SuperClusters
SuperClusters
DirectConnect
No antifuses
0.1 ns routing delay
FastConnect
One antifuse
0.5 ns routing delay
Routing Segments
Typically 2 antifuses
Max. 5 antifuses
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EX256-TQ100I | 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| EX256-TQ100PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs |
| EX256-TQG100 | 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| EX256-TQG100A | 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| EX256-TQG100I | 功能描述:IC FPGA ANTIFUSE 12K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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