參數(shù)資料
型號： FS451AC
廠商： Electronic Theatre Controls, Inc.
英文描述： i-Net TV Interface Video Processor
中文描述： 一至網(wǎng)絡(luò)電視接口視頻處理器
文件頁數(shù)： 52/60頁
文件大?。?/td> 266K
代理商： FS451AC
FS450, FS451
PRELIMINARY PRODUCT DESCRIPTION
JUNE, 2000, VERSION 1.2
52
COPYRIGHT
ó
1999, 2000 FOCUS ENHANCEMENTS, INC.
PRELIMINARY INFORMATION
7. Design and Layout Considerations
Careful circuit design and layout are key factors that insure a successful implementation of the FS450 in a
product. The following guidelines will help insure that your design yields the best possible results.
7.1 Pixel Phase Lock Loop
The analog supply for the Pixel PLL should always be clean and noise free to insure minimum jitter in
the PLL. Do not power other circuitry from the PLL supply.
The supply line V
DDPA
should be decoupled with a series resistor of 150
W
and a 4.7
μ
F tantalum
capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100
μ
F. Always have a 1000pF to 0.1
μ
F
capacitor to remove high frequency noise.
Use a solid ground plane under the FS450.
7.2 Video Output Filters
To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75
W
termination resistors and the first capacitor of the output filter close to the video output pins of the
FS450.
7.3 Analog Power Supply Bypassing, Filtering, and Isolation
When possible, it is recommended that the analog supply voltages be fed from a linear voltage regulator.
Switching power supply noise, and noise from the digital plane can induce visible artifacts into the
displayed video. Always provide sufficient filtering and high frequency bypassing to insure that power
supply noise is minimized for visual as well as EMI reasons.
It is recommended that each power supply section be isolated with a ferrite bead and a 4.7
μ
F capacitor.
Where the power pins are so close together that the 0.1
μ
F bypass capacitors are adjacent, consider
changing one of the adjacent capacitors to 100 to 1000pF to reduce higher frequency noise on the
power supply.
7.4 Power and Ground
Within the FS450, separate power is routed to functional sections: phase locked loop, D/A converters,
digital processors and digital drivers. All ground pins should be connected to a common ground plane.
Power pins should be segregated into analog and digital sections.
Clean analog power should be applied to the V
DDPA
, V
DDOSC
, and V
DDDA
pins. A 0.1
μ
F capacitor should
be placed adjacent to each group of pins. The capacitor connected to C
BYPASS
is critical, and it must be
connected to V
DDDA
to minimize noise at the D/A converter outputs. Chip capacitors are recommended.
Digital power may be derived from system digital +3.3 volts. If necessary insert a ferrite bead in series
with the supply trace. A 47
μ
F capacitor should be placed across the common +3.3 VDC for V
DD
and
V
DDDA
to act as a reservoir for heavy currents drawn by D/A converters and internal memories. At least
one 0.1
μ
F capacitor should be located adjacent to V
DD
pins along each side of the FS450 to supply
transient currents.
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