參數(shù)資料
型號: FW802A
英文描述: Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
中文描述: 低功耗PHY的IEEE 1394A端口- 2000兩線收發(fā)器/仲裁器裝置
文件頁數(shù): 28/36頁
文件大小: 461K
代理商: FW802A
Intel
80200 Processor based on Intel
XScale
Microarchitecture
Electrical Specifications
28
August 2002
Datasheet
4.4.2
Bus Signal Timings
Table 14.
Output Timings
Symbol
Parameter
Min
Max
Units
Notes
T
OV1
Output valid delay from
MCLK
--
D[63:0], DCB,
and
BE#
1.5
6.9
ns
(1, 2)
T
OF1
Output float delay from
MCLK
--
D[63:0]
,
DCB,
and
BE#
1.1
6.0
ns
(1, 2, 3)
T
OS1
Output Slew Rate --
D[63:0],
DCB,
and
BE#
1.0
4.0
V/ns
0.4 V to 2.4 V (1, 2, 4)
T
OV2
Output valid delay from
MCLK
--
A[15:0], HLDA, W/R#, LOCK,
and
ADS#
1.5
6.8
ns
(1, 2, 4)
T
OF2
Output float delay from
MCLK
--
A[15:0], HLDA, W/R#, LOCK,
ADS#, RESETOUT#,
and
PWRSTATUS
1.1
6.0
ns
(1, 2, 3, 4)
T
OS2
Output Slew Rate --
A[15:0],
HLDA, W/R#, LOCK, ADS#,
RESETOUT#,
and
PWRSTATUS
1.0
4.0
V/ns
0.4 V to 2.4 V (1, 2, 4)
NOTES:
1. Minimum values characterized with a 10 pF load at 3.6 V, 0
°
C
2. Maximum values characterized with a 30 pF load at 2.9 V., 110
°
C
3. Pin is floating when its output falls to I
LO
4. Not tested
Table 15.
Input Timings
Symbol
Parameter
Min
Max
Units
Notes
T
IS
Input setup time to
MCLK
--
ABORT, CWF, DVALID, D,
and
DCB
1.2
ns
T
IH
Input hold time from
MCLK
--
ABORT, CWF, DVALID, D,
and
DCB
1.5
ns
T
ISH
Input setup time to
MCLK
--
HOLD
1.3
ns
T
IHH
Input hold time from
MCLK
--
HOLD
0.9
ns
相關(guān)PDF資料
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FW802A-DB Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
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