參數(shù)資料
型號： FW802C
英文描述： FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
中文描述： 防火墻802C低-動力IEEE 1394A端口- 2000兩艘電纜收發(fā)器/仲裁器裝置
文件頁數(shù)： 1/24頁
文件大小： 301K
代理商： FW802C
Data Sheet, Rev. 1
October 2002
FW802C Low-Power PHY IEEE
1394A-2000
Two-Cable Transceiver/Arbiter Device
Distinguishing Features
I
Compliant with IEEEStandard 1394a-2000, IEEE
Standard for a High Performance Serial Bus
Amendment 1.
I
Low-power consumption during powerdown or
microlow-power sleep mode.
I
Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
I
While unpowered and connected to the bus, the
device will not drive TPBIAS on a connected port
even if receiving incoming bias voltage on that port.
I
Does not require external filter capacitors for PLL.
I
Does not require a separate 5 V supply for 5 V link
controller interoperability.
I
Interoperable across 1394
cable with 1394physi-
cal layers (PHY) using 5 V supplies.
I
Interoperable with 1394link-layer controllers using
5 V supplies.
I
1394a-2000 compliant common-mode noise filter
on incoming TPBIAS.
I
Powerdown features to conserve energy in battery-
powered applications include:
— Device powerdown pin.
— Link interface disable using LPS.
— Inactive ports powerdown.
— Automatic microlow-power sleep mode during
suspend.
I
Interface to link-layer controller supports Annex J
electrical isolation as well as bus-keeper isolation.
Features
I
Provides two compliant cable ports at 100 Mbits/s,
200 Mbits/s, and 400 Mbits/s.
I
Supports OHCI requirements.
I
Supports arbitrated short bus reset to improve
utilization of the bus.
I
Supports ack-accelerated arbitration and fly-by con-
catenation.
I
Supports connection debounce.
I
Supports multispeed packet concatenation.
I
Supports PHY pinging and remote PHY access
packets.
I
Supports full suspend/resume.
I
Supports PHY-link interface initialization and reset.
I
Supports
1394
a-2000 register set.
I
Supports LPS/link-on as a part of PHY-link inter-
face.
I
Supports provisions of
IEEE
1394
-1995
Standard
for a High Performance Serial Bus
.
I
Fully interoperable with
FireWire
implementation
of IEEE1394-1995.
I
Reports cable power fail interrupt when voltage at
CPS pin falls below 7.5 V.
I
Separate cable bias and driver termination voltage
supply for each port.
I
Meets Intel
Mobile Power Guideline 2000
Other Features
I
48-pin TQFP package.
I
Single 3.3 V supply operation.
I
Data interface to link-layer controller provided
through 2/4/8 parallel lines at 50 Mbits/s.
I
25 MHz crystal oscillator and PLL provide transmit/
receive data at 100 Mbits/s, 200 Mbits/s, and
400 Mbits/s, and link-layer controller clock at
50 MHz.
I
Node power-class information signaling for system
power management.
I
Multiple separate package signals provided for ana-
log and digital supplies and grounds.
相關PDF資料
PDF描述
FW802C-DB FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
FW803-09-DB PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
FW803 PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
FW804-09-DB PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device
FW804 PHY IEEE 1394A Four-Cable Transceiver/Arbiter Device
相關代理商/技術參數(shù)
參數(shù)描述
FW802C-DB 制造商:AGERE 制造商全稱:AGERE 功能描述:FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
FW803 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
FW803-09-DB 制造商:AGERE 制造商全稱:AGERE 功能描述:PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
FW80321M400 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:80321 I/O Processor
FW80321M400SL6R2 功能描述:IC I/O PROCESSOR CMOS 544BGA PKG RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:40 系列:MPC83xx 處理器類型:32-位 MPC83xx PowerQUICC II Pro 特點:- 速度:267MHz 電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 封裝/外殼:516-BBGA 裸露焊盤 供應商設備封裝:516-PBGAPGE（27x27） 包裝:托盤
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