參數(shù)資料
型號(hào): GS8161Z36D-200I
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 512K X 36 ZBT SRAM, 6.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁數(shù): 14/36頁
文件大?。?/td> 939K
代理商: GS8161Z36D-200I
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
21/36
1998, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max Min Max Min Max
Pipeline
Clock Cycle Time
tKC
4.0
4.4
5.0
6.0
6.7
7.5
ns
Clock to Output Valid
tKQ
2.5
2.7
3.0
3.4
3.8
4.0
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ1
1.5
1.5
1.5
1.5
1.5
1.5
ns
Setup time
tS
1.2
1.3
1.4
1.5
1.5
1.5
ns
Hold time
tH
0.2
0.3
0.4
0.5
0.5
0.5
ns
Flow
Through
Clock Cycle Time
tKC
5.5
6.0
6.5
7.0
7.5
8.5
ns
Clock to Output Valid
tKQ
5.5
6.0
6.5
7.0
7.5
8.5
ns
Clock to Output Invalid
tKQX
3.0
3.0
3.0
3.0
3.0
3.0
ns
Clock to Output in Low-Z
tLZ1
3.0
3.0
3.0
3.0
3.0
3.0
ns
Setup time
tS
1.5
1.5
1.5
1.5
1.5
1.5
ns
Hold time
tH
0.5
0.5
0.5
0.5
0.5
0.5
ns
Clock HIGH Time
tKH
1.3
1.3
1.3
1.3
1.5
1.7
ns
Clock LOW Time
tKL
1.5
1.5
1.5
1.5
1.7
2
ns
Clock to Output in
High-Z
tHZ1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
2.3
2.5
3.2
3.5
3.8
4.0
ns
G to output in Low-Z
tOLZ1
0
0
0
0
0
0
ns
G to output in High-Z
tOHZ1
2.3
2.5
3.0
3.0
3.0
3.0
ns
ZZ setup time
tZZS2
5
5
5
5
5
5
ns
ZZ hold time
tZZH2
1
1
1
1
1
1
ns
ZZ recovery
tZZR
20
20
20
20
20
20
ns
相關(guān)PDF資料
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GS8161Z36T-166T 512K X 36 ZBT SRAM, 7 ns, PQFP100
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