參數資料
型號： GS832236B-225
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 1M X 36 CACHE SRAM, 7 ns, PBGA119
封裝： 14 X 22 MM, 1.27 MM PITCH, FBGA-119
文件頁數： 26/46頁
文件大?。?/td> 1592K
代理商： GS832236B-225
GS832218(B/E)/GS832236(B/E)/GS832272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.07a 12/2007
32/46
2001, GSI Technology
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
相關PDF資料
PDF描述
GS832236E-225IV 1M X 36 CACHE SRAM, 7 ns, PBGA165
GS8322Z18E-225VT 2M X 18 ZBT SRAM, 7 ns, PBGA165
GS8322ZV72GC-150IT 512K X 72 ZBT SRAM, 8.5 ns, PBGA209
GS8322ZV36GB-200T 1M X 36 ZBT SRAM, 7.5 ns, PBGA119
GS8322ZV36GE-225IT 1M X 36 ZBT SRAM, 7 ns, PBGA165
相關代理商/技術參數
參數描述
GS832236B-250 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 6.5NS/2.5NS 119FBGA - Trays
GS832236E-150 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 8.5NS/3.8NS 165FBGA - Trays
GS832236E-150I 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 2.5V/3.3V 36MBIT 1MX36 8.5NS/3.8NS 165FBGA - Trays
GS832236E-150IT 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 36MBIT 1MX36 8.5NS/3.8NS 165FBGA - Tape and Reel
GS832236E-150IV 制造商:GSI Technology 功能描述:SRAM SYNC QUAD 1.8V/2.5V 36MBIT 1MX36 8.5NS/3.8NS 165FPBGA - Trays
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*