- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296050 > GT25C32-2UDLI-TR (GIANTEC SEMICONDUCTOR INC) 4K X 8 SPI BUS SERIAL EEPROM, DSO8 PDF資料下載
參數(shù)資料
| 型號(hào)： | GT25C32-2UDLI-TR |
| 廠商： | GIANTEC SEMICONDUCTOR INC |
| 元件分類： | PROM |
| 英文描述： | 4K X 8 SPI BUS SERIAL EEPROM, DSO8 |
| 封裝： | 2 X 3 MM, GREEN, MO-229, DFN-8 |
| 文件頁(yè)數(shù)： | 11/18頁(yè) |
| 文件大?。?/td> | 781K |
| 代理商： | GT25C32-2UDLI-TR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
2
Integrated Silicon Solution, Inc. — www.issi.com
Advanced Information Rev. 00C
07/16/09
IS25C32B
Write Protect (WP): The purpose of this input signal is
to initiate Hardware Write Protection mode. This mode
prevents the Block Protection bits and the WPEN bit in
the Status Register from being altered. To cause Hard-
ware Write Protection, WP must be Low at the same
time WPEN is 1. WP may be hardwired to Vcc or GND.
HOLD (HOLD): This input signal is used to suspend
the device in the middle of a serial sequence and tem-
porarily ignore further communication on the bus (SI,
SO, SCK). Together with Chip Select, the HOLD signal
allows multiple slaves to share the bus. The HOLD
signal transitions must occur only when SCK is Low,
and be held stable during SCK transitions. (See Figure
8 for Hold timing) To disable this feature, HOLD may be
hardwired to Vcc.
PIN DESCRIPTIONS
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
Vcc
Power
WP
Write Protect
HOLD
Suspends Serial Input
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides
synchronization between the microcontroller and
IS25C32B. Op-Codes, byte addresses, and data are
latched on SI with a rising edge of the SCK. Data on
SO is refreshed on the falling edge of SCK for SPI
modes (0,0) and (1,1).
Serial Data Input (SI): This is the input pin for all data
that the IS25C32B is required to receive.
Serial Data Output (SO): This is the output pin for all
data transmitted from the IS25C32B.
PIN CONFIGURATION
8-Pin DIP, SOIC, and TSSOP
Chip Select (CS): The CS pin activates the device.
Upon power-up, CS should follow Vcc. When the de-
vice is to be enabled for instruction input, the signal re-
quires a High-to-Low transition. While CS is stable Low,
the master and slave will communicate via SCK, SI, and
SO signals. Upon completion of communication, CS
must be driven High. At this moment, the slave device
may start its internal write cycle. When CS is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8-pad DFN
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GT3020/L2C-B45562C4CB2/2T | SINGLE COLOR LED, COOL WHITE, 2.7 mm |
| GTXO-72T/FCK19.20MHZ | TCXO, CLIPPED SINE OUTPUT, 19.2 MHz |
| GTXO-72T/FCL19.80MHZ | TCXO, CLIPPED SINE OUTPUT, 19.8 MHz |
| GTXO-72T/FCP20.0MHZ | TCXO, CLIPPED SINE OUTPUT, 20 MHz |
| GTXO-72T/FRM16.80MHZ | TCXO, CLIPPED SINE OUTPUT, 16.8 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT25G101 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:SILICON N−CHANNEL IGBT STROBE FLASH APPLICATIONS |
| GT25G101(Q) | 功能描述:IGBT 晶體管 IGBT 400V 170A RoHS:否 制造商:Fairchild Semiconductor 配置: 集電極—發(fā)射極最大電壓 VCEO:650 V 集電極—射極飽和電壓:2.3 V 柵極/發(fā)射極最大電壓:20 V 在25 C的連續(xù)集電極電流:150 A 柵極—射極漏泄電流:400 nA 功率耗散:187 W 最大工作溫度: 封裝 / 箱體:TO-247 封裝:Tube |
| GT25G101(SM) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | IGBT | N-CHAN | 400V V(BR)CES | 25A I(C) | TO-263VAR |
| GT25G101_06 | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:SILICON N−CHANNEL IGBT STROBE FLASH APPLICATIONS |
| GT25G101SM | 制造商:TOSHIBA 制造商全稱:Toshiba Semiconductor 功能描述:N CHANNEL IGBT (STROBE FLASH APPLICATIONS) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。