參數(shù)資料
型號(hào)： HC05J5GRS
英文描述： 68HC05J5 General Release Specification
中文描述： 68HC05J5一般版本規(guī)范
文件頁(yè)數(shù)： 20/106頁(yè)
文件大?。?/td> 1366K
代理商： HC05J5GRS
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
2-2
MEMORY
MC68HC05J5A
REV 2.1
2.1
I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000-$001F. The overall orga-
nization of these registers is shown in
Figure 2-2
. The bit assignments for each
register are shown in
Figure 2-3
and
Figure 2-4
. Reading from unimplemented
bits will return unknown states, and writing to unimplemented bits will be ignored.
Figure 2-2. I/O Registers Memory Map
2.2
RAM
The total RAM consists of 128 bytes (including the stack) at locations $0080
through $00FF. The stack begins at address $00FF and proceeds down to $00C0.
Using the stack area for data storage or temporary work locations requires care to
prevent it from being overwritten due to stacking from an interrupt or subroutine
call.
2.3
ROM
There are a total of 2570 bytes of user ROM on-chip. This includes 2560 bytes of
user ROM from locations $0300 to $0CFF for user program storage and 10 bytes
for user vectors from locations $0FF6 to $0FFF.
Port A Data Register
$0000
Port B Data Register
$0001
Port A Data Direction Register
$0004
Port B Data Direction Register
unimplemented (2)
$0005
MFT Control & Status Register
$0008
MFT Counter Register
$0009
Reserved for Test
$001F
unimplemented (5)
IRQ Control & Status Register
$000A
Port A Pulldown/up Register
$0010
Port B Pulldown/up Register
$0011
unimplemented (1)
$0002
$0003
unimplemented (2)
Timer1 Registers (4)
$0012
$0015
unimplemented (3)
Timer1 Registers (4)
$0018
$001B
$001E
Reserved
Timer1 Capture Control Register
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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