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參數(shù)資料
| 型號： | HC05J5GRS |
| 英文描述： | 68HC05J5 General Release Specification |
| 中文描述： | 68HC05J5一般版本規(guī)范 |
| 文件頁數(shù)： | 55/106頁 |
| 文件大?。?/td> | 1366K |
| 代理商： | HC05J5GRS |
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July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
MULTI-FUNCTION TIMER
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
8-3
8.3.1 Timer Counter Register (TCR) $09
The Timer Counter Register is a read-only register which contains the current
value of the 8-bit ripple counter at the beginning of the timer chain. This counter is
clocked at f
op
divided by 4 and can be used for various functions including a soft-
ware input capture. Extended time periods can be attained using the TOF function
to increment a temporary RAM storage location thereby simulating a 16-bit (or
more) counter. The value of each bit of the TCR is shown in
Figure 8-3
. This reg-
ister is cleared by reset.
Figure 8-3. Timer Counter Register
8.3.2 Timer Control/Status Register (TCSR) $08
The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and
the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will
read as logical zeros.
Figure 8-4
shows the value of each bit in the TCSR follow-
ing reset.
Figure 8-4. Timer Control/Status Register (TCSR)
TOF - Timer Overflow Flag
The TOF is a read-only flag bit.
1 =
Set when the 8-bit ripple counter rolls over from $FF to $00. A
TIMER Interrupt request will be generated if TOFE is also set.
0 =
Reset by writing a logical one to the TOF acknowledge bit, TOFR.
Writing to the TOF flag bit has no effect on its value. This bit is
cleared by reset.
TCR
$09
0
7
W
R
0
0
0
0
0
0
0
Reset
6
5
4
3
2
1
0
TMR0
TMR2
TMR1
TMR3
TMR4
TMR5
TMR6
TMR7
RTIF
TOFE
0
7
TOF
RT1
W
R
0
0
0
0
0
1
1
6
5
4
3
2
1
0
TCSR
$08
Reset
0
RTIFR
0
TOFR
RTIE
RT0
F
Freescale Semiconductor, Inc.
n
.
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