Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
Block Diagram of A/D Converter.........................................................................208
The Response of the A/D Converter.....................................................................214
A/D Operation in Single Mode (When Channel 1 is Selected).............................216
A/D Operation in Scan Mode (When Channel 0 to 2 are Selected)......................219
A/D Conversion Timing........................................................................................221
External Trigger Input Timing ..............................................................................222
Figure 11-1
Figure 11-2
Figure 11-3
Figure 11-4
Block Diagram of Dual-Port RAM.......................................................................226
Parallel Communication Data Register 0..............................................................230
Dual-Port RAM Timing Chart ..............................................................................236
Interconnection to H8/532 (Example)...................................................................237
Figure 12-1
Block Diagram of On-Chip RAM.........................................................................239
Figure 13-1
Figure 13-2
Figure 13-3
Figure 13-4
Figure 13-5
Figure 13-6
Block Diagram of On-Chip ROM.........................................................................242
Socket Adapter Pin Assignments..........................................................................244
Memory Map in PROM Mode..............................................................................245
High-Speed Programming Flowchart....................................................................246
PROM Write/Verify Timing..................................................................................248
Recommended Screening Procedure.....................................................................249
Figure 14-1
Figure 14-2
Software Standby Mode (when) NMI Timing......................................................258
Hardware Standby Mode Timing..........................................................................260
Figure 15-1
Execution Cycle of Instruction Synchronized with E Clock in
Expanded Modes (Maximum Synchronization Delay).........................................262
Execution Cycle of Instruction Synchronized with E Clock in
Expanded Modes (Minimum Synchronization Delay)..........................................263
Figure 15-2
Figure 16-1
Figure 16-2
Figure 16-3
Figure 16-4
Figure 16-5
Figure 16-6
Block Diagram of Clock Pulse Generator.............................................................265
Connection of Crystal Oscillator (Example).........................................................266
Equivalent Circuit of External Crystal..................................................................266
Notes on Board Design around External Crystal..................................................267
External Clock Input (Example) ...........................................................................267
Phase Relationship of System Clock and E Clock................................................268
Figure 17-1
Figure 17-2
Example of Circuit for Driving a Darlington Pair.................................................272
Example of Circuit for Driving a LED..................................................................272
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