參數(shù)資料
型號: HD66326T
廠商: Hitachi,Ltd.
英文描述: Multiscan XGA/SXGA High-Quality 64-Gradation TFT Liquid Crystal Driver(TFT LCD驅(qū)動器)
中文描述: 多掃描的XGA / SXGA的高品質(zhì)64分等TFT液晶驅(qū)動(TFT液晶驅(qū)動器)
文件頁數(shù): 15/29頁
文件大小: 430K
代理商: HD66326T
HD66326T
15
Operation Timing
CL2
D5j
CL4
EIO0L
(NO.1)
Y1 to Y384
EIO0L
(NO.8)
EIO0R
1
2
513
514
3
4
64
65
66
512
513
514
515
INVALID
d3072
IC (No. 1) data latch period
IC (No. 2) data latch period
IC (No. 8) data latch period
Line
When SHL = V
CC
d372
d384
INVALID
d3072
d3060
D4j
INVALID
d3071
d371
d383
INVALID
d3071
d3059
D3j
INVALID
d3070
d370
d382
INVALID
d3070
d3058
D2j
INVALID
d3069
d369
d381
INVALID
d3069
d3057
D1j
INVALID
d3068
d368
d380
INVALID
d3068
d3056
D0j
INVALID
d3067
d367
d379
INVALID
d3067
d3055
POL
INVALID
INVALID
d6
d12
d5
d11
d4
d10
d3
d9
d2
d8
d1
d7
d3066
d3065
d3064
d3063
d3062
d3061
d378
d377
d376
d375
d374
d373
The high level of the enable input signal (when SHL = V
CC
: EIO0R) is latched on the rising edge of the
CL2 data latch clock signal, and data latching begins after two CL2 signal cycles. Data latching is
performed simultaneously for 6 bits
×
RGB
×
2 pixels, i.e. data for 6 outputs, on the rising edge of the CL2
signal. On the rising edge of the 65th CL2 signal clock pulse, the enable output signal (when SHL = V
CC
:
EIO0L) is driven high, and the operation is halted (standby state entered) automatically when latching of
data is completed for 384 outputs. By connecting the EIO0L pin to the next-stage EIO0R pin, the next-
stage IC is activated in the same way. All the IC enable output signals are reset on the rising edge of the
CL4 signal.
The CL2 data latch clock signal does not require a clock-stoppage period. At least three CL2 clocks more
than the necessary number (512 clocks for XGA) should be input in one horizontal period.
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HD66330T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver
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HD66339 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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