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參數(shù)資料
| 型號(hào)： | HD66410 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | RAM-Provided 128-Channel Driver for Dot-Matrix Graphic LCD(點(diǎn)陣圖形LCD128通道驅(qū)動(dòng)器) |
| 中文描述： | 內(nèi)存提供128通道驅(qū)動(dòng)點(diǎn)陣圖形LCD（點(diǎn)陣圖形LCD128通道驅(qū)動(dòng)器） |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 177K |
| 代理商： | HD66410 |
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HD66410
18
Access to Internal Registers and Display RAM
Access to Internal Registers by the MPU:
The internal registers include the index register and data
registers. The index register can be accessed by driving both the
CS
and RS signals low. To access a data
register, first write its register number to the index register with RS set to 0, and then access the data
register with RS set to 1. Once written, the register number is held until it is rewritten, enabling the same
register to be consecutively accessed without having to rewrite to the register number for each access.
Some data registers contain unused bits; they should be set to 0. Note that all data registers except the
display memory access register can only be written to.
Access to Display RAM by the MPU:
To access the display RAM, first write the RAM address desired to
the X address register (R2) and the Y address register (R3). Then read/write the display memory access
register (R4). Memory access by the MPU is independent of memory read by the HD66410 and is also
asynchronous with the system clock, thus enabling an interface independent of HD66410’s internal
operations. However, when reading, data is temporarily latched into a HD66410’s buffer and then output
next time a read is performed in a subsequent cycle. This means that a dummy read is necessary after
setting X and Y addresses. The memory read sequence is shown in Figure 10.
X and Y addresses are automatically incremented after each memory access according to the INC bit value
in control register 2; therefore, it is not necessary to update the addresses for each access. Figure 11 shows
two cases of incrementing display RAM address. When the INC bit is 0, the Y address will be incremented
up to H’3F with the X address unchanged. However, actual memory is valid only within H’00 to H’20;
accessing an invalid address is ignored. When the INC bit is 1, the X address will be incremented up to H’F
with the Y address unchanged. After address H’F, the X address will return to H’0; if more than 16 bytes of
data are consecutively written, data will be overwritten at the same address.
RS
WR
RD
Input
data
Output
data
Undetermined
Dummy read
H'02
[n]
H'03
[m]
H'04
X address
Y address
Data[n,m]
Data[n,m+1]
Figure 10 Display RAM Read Sequence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD66420 | (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66420TA0 | LCD Display Driver |
| HD66421 | (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66421TB0 | (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66503 | 240-Channel Common Driver with Internal LCD Timing Circuit(帶內(nèi)部LCD定時(shí)電路的240通道驅(qū)動(dòng)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD66420 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:(RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66420TA0 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCD Display Driver |
| HD66421 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:(RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66421TB0 | 制造商:Renesas Electronics Corporation 功能描述: |
| HD66503 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
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