- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370471 > HD66410 (Hitachi,Ltd.) RAM-Provided 128-Channel Driver for Dot-Matrix Graphic LCD(點陣圖形LCD128通道驅(qū)動器) PDF資料下載
參數(shù)資料
| 型號： | HD66410 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | RAM-Provided 128-Channel Driver for Dot-Matrix Graphic LCD(點陣圖形LCD128通道驅(qū)動器) |
| 中文描述： | 內(nèi)存提供128通道驅(qū)動點陣圖形LCD（點陣圖形LCD128通道驅(qū)動器） |
| 文件頁數(shù)： | 35/50頁 |
| 文件大?。?/td> | 177K |
| 代理商： | HD66410 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
HD66410
35
Internal Registers
The HD66410 has one index register and 22 data registers, all of which can be accessed asynchronously
with the internal clock. All the registers except the display memory access register are write-only.
Accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to.
Index Register (IR):
The index register (Figure 26) selects one of 22 data registers. The index register
itself is selected when both the
CS
and RS signals are low. Data bits 7 to 5 are unused; they should be set to
0 when written to.
Control Register 1 (R0):
Control register 1 (Figure 27) controls general operations of the HD66410. Each
bit has its own function as described below. Data bit 7 bit is unused; it should be set to 0 when written to.
DSP bit
DSP = 1: Display on
DSP = 0: Display off (all LCD driver output pins output V
CC
level)
STBY bit
STBY = 1: Internal operation and booster halt; display off
STBY = 0: Normal operation
The STBY bit does not affect the state of PWR and DISP bit.
PWR bit
PWR = 1: Booster active
PWR = 0: Booster inactive
OSC bit
OSC = 1: Internal operation and booster halt; oscillator does not halt to provide annunciator display
OSC = 0: Internal operation, booster, and oscillator halt
The OSC bit is valid only when the STBY bit is 1.
IDTY bit
IDTY = 1: Annunciator display signals are operating statically
IDTY = 0: Annunciator display signals are operating with 1/3 duty cycle
CNF bit
CNF = 1: Row output on both sides of the LCD panel
CNF = 0: Row output on one side of the LCD panel
ADC bit
ADC = 1: Data in X address H’0 is output from X128 or X144; row signals are scanned from X129 to
X161.
ADC = 0: Data in X address H’0 is output from X1 or X17; row signals are scanned from X161 to
X129.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HD66420 | (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66420TA0 | LCD Display Driver |
| HD66421 | (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66421TB0 | (RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66503 | 240-Channel Common Driver with Internal LCD Timing Circuit(帶內(nèi)部LCD定時電路的240通道驅(qū)動器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HD66420 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:(RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66420TA0 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:LCD Display Driver |
| HD66421 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:(RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD) |
| HD66421TB0 | 制造商:Renesas Electronics Corporation 功能描述: |
| HD66503 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD Display Driver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。