583
FLER bit setting conditions are as follows:
When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
Immediately after exception handling (excluding a reset) during programming/erasing
When a SLEEP instruction (including software standby) is executed during
programming/erasing
When the CPU loses the bus during programming/erasing
Error protection is released only by a reset and in hardware standby mode.
Figure 17.23 shows the flash memory state transition diagram.
RD
VF
PR ER FLER = 0
Error
occurrence
RES
= 0 or
STBY
= 0
RES
= 0 or
STBY
= 0
RD
VF
PR
ER
FLER = 0
Normal operating mode
Program mode
Erase mode
Reset or hardware standby
(hardware protection)
RD VF
PR
ER
FLER = 1
RD
VF
PR
ER
FLER = 1
Error protection mode
Error protection mode
(software standby)
Software
standby mode
FLMCR1, FLMCR2 (except FLER
bit), EBR1, EBR2 initialization state
FLMCR1, FLMCR2,
EBR1, EBR2
initialization state
Software standby
mode release
RD:
VF:
PR:
ER:
Memory read possible
Verify-read possible
Programming possible
Erasing possible
RD
:
VF
:
PR
:
ER
:
Memory read not possible
Verify-read not possible
Programming not possible
Erasing not possible
Legend:
RES
= 0 or
STBY
= 0
Error occurrence
(software standby)
Memory
read verify mode
RD VF
PR
ER
FLER = 0
RES
= 0 or
STBY
= 0
or software standby
Reset release and
hardware standby release
and software standby release
P = 1 or
E = 1
P = 0 and
E = 0
Figure 17.23 Flash Memory State Transitions