825
SSR1—Serial Status Register 1
H'FF84
Smart Card Interface 1
7
TDRE
1
R/(W)
*
6
RDRF
0
R/(W)
*
5
ORER
0
R/(W)
*
4
ERS
0
R/(W)
*
3
PER
0
R/(W)
*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Note:
*
Can only be written with 0 for flag clearing.
Transmit Data Register Empty
0
Receive Data Register Full
0
Overrun Error
0
Error Signal Status
0
Parity Error
0
Transmit End
0
Multiprocessor Bit
[Clearing condition]
When data with a 0 multiprocessor bit is received
Multiprocessor Bit Transfer
0
1
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
Bit
Initial value
Read/Write
:
:
:
[Setting conditions]
When data with a 1 multiprocessor bit is received
[Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
On reset, or in standby mode or module stop mode
When the TE bit in SCR is 0 and the ERS bit is 0
When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu
after a 1-byte serial character is transmitted when GM = 0
When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu
after a 1-byte serial character is transmitted when GM = 1
1
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/
E
bit in SMR
1
[Clearing condition]
On reset, or in standby mode or module stop mode
When 0 is written to ERS after reading ERS =1
[Setting conditions]
When the error signal is sampled at the low level
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
[Clearing condition]
When 0 is written to RDRF after reading RDRF = 1
When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
[Clearing condition]
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting condition]
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR
Note: etu: Elementary Time Unit (the time taken to transmit one bit)
1
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
1
1
1
0
1