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參數(shù)資料
| 型號： | HFCT-5202 |
| 英文描述： | 155 Mb/s Single Mode Fiber Transceiver with Integrated Clock and Data Recovery for ATM, SONET OC-3/SDH STM-1(應(yīng)用于ATM, SONET OC-3/SDH STM-1帶集成時鐘和數(shù)據(jù)恢復(fù)的155 Mb/s單模式光收發(fā)器) |
| 中文描述： | 155 Mb / s的對ATM，SONET的OC-3/SDH的STM - 1單模光纖收發(fā)器（應(yīng)用于自動取款機(jī)，SONET的OC-3/SDH的STM - 1帶集成時鐘和數(shù)據(jù)恢復(fù)的155 MB的集成的時鐘和數(shù)據(jù)恢復(fù)/擰單模式光收發(fā)器） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 170K |
| 代理商： | HFCT-5202 |
10
Table 2. Pin Out Table
Pin
Symbol
Mounting
Studs
Functional Description
The mounting studs are provided for transceiver mechanical attachment to the circuit
board. They are embedded in the nonconductive plastic housing and are not connected
to the transceiver internal circuit. They should be soldered into plated-through holes
on the printed circuit board.
Reference Clock - Optional Feature
Reference Clock can be used as an optional, internally generated local receiver clock
when the Input Optical Signal is disrupted. See Pin 2 Lck Ref- description. This input
is not required for the normal operation of the Clock recovery circuit. This is a single-
ended PECL input.
1
Ref Clk
If this Reference Clock input is used, provide a 19.44 MHz external reference clock
signal and terminate at this input pin with standard PECL techniques.
If this Reference Clock input is not used, leave the input open-circuited. With the input
open-circuited, an internal pull-down resistor will bias this input to a low-state
condition.
Lock-to-Reference Clock Bar - Optional Feature
Lock-to-Reference Clock Bar can be used to help manage the performance of the
receiver when the Input Optical Signal is disrupted. When used, it places the received
data outputs in static states and it triggers an internally generated local receiver clock
to be output on Clk/Clk- in substitution of recovered clock. This is a single-ended
PECL input.
2
Lck Ref–
For normal operation of the transceiver, connect this Lock-to-Reference-bar input to
V
CC
or a PECL high-state (V
IH
) which causes the internal CDR circuit to output
recovered differential clock on Clk/Clk- and re-timed differential data on RD/RD-.
For optional use to make static the received data outputs and to output the internally
generated local receiver clock, connect Lck Ref- input to a PECL low-state (V
IL
), or
leave this input open-circuited. When this is done it will cause: 1) the Received Data
outputs to change to static PECL logic levels (RD = V
OL
and RD- = V
OH
), 2) the internal
CDR circuit to switch over to using the external reference clock, if provided, as the
timing source to generate a 155.52 Mb/s clock output on Clk/Clk-. If the feature is used,
one way to implement it is to connect this pin to Signal Detect directly with a single
pull-down resistor of 10 k
to ground.
If this Lock-to-Reference feature is not used, this pin must be connected directly to
V
CC
or a PECL high-state to disable it.
Received Recovered Clock Out Bar
See pins 1 & 2 for optional, local generated clock output.
3
Clk–
The rising edge occurs coincident with the edges of the Received Data output.
The falling edge occurs in the middle of the Received Data baud period.
Terminate this high-speed, differential clock output with standard PECL techniques at
the clock input point of the follow-on device.
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