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參數(shù)資料
| 型號： | HFCT-5202 |
| 英文描述： | 155 Mb/s Single Mode Fiber Transceiver with Integrated Clock and Data Recovery for ATM, SONET OC-3/SDH STM-1(應用于ATM, SONET OC-3/SDH STM-1帶集成時鐘和數(shù)據(jù)恢復的155 Mb/s單模式光收發(fā)器) |
| 中文描述： | 155 Mb / s的對ATM，SONET的OC-3/SDH的STM - 1單模光纖收發(fā)器（應用于自動取款機，SONET的OC-3/SDH的STM - 1帶集成時鐘和數(shù)據(jù)恢復的155 MB的集成的時鐘和數(shù)據(jù)恢復/擰單模式光收發(fā)器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 170K |
| 代理商： | HFCT-5202 |
4
better BER condition than
1 x 10
-10
, more input signal is
needed (+dB).
Recommended Circuit
Schematic
In order to insure proper
functionality of the HFCT-5202 a
recommended circuit is provided
in Figure 4. When designing the
circuit interface, there are a few
fundamental guidelines to follow.
For example, in the Recom-
mended Circuit Schematic figure
the differential data lines should
be treated as 50 ohm Microstrip
or stripline transmission lines.
This will help to minimize the
parasitic inductance and capaci-
tance effects. Proper termination
of the differential data and clock
signals will prevent reflections
and ringing which would
compromise the signal fidelity
and generate unwanted electrical
noise. Locate termination at the
received signal end of the
transmission line. The length of
these lines should be kept short
and of equal length to prevent
pulse-width distortion and data-
to-clock timing skew from
occurring. For the high speed
signal lines, differential signals
should be used, not single-ended
signals, and these differential
signals need to be loaded sym-
metrically to prevent unbalanced
currents from flowing which will
cause distortion in the signal.
Maintain a solid, low inductance
ground plane for returning signal
currents to the power supply.
Multilayer plane printed circuit
board is best for distribution of
V
CC
, returning ground currents,
forming transmission lines and
shielding. Also, it is important to
suppress noise from influencing
the fiber-optic transceiver
performance, especially the
Figure 4. Recommended Circuit Schematic.
receiver and the clock recovery
circuits. Proper power supply
filtering of V
CC
for this
transceiver is accomplished by
using the recommended, separate
filter circuits shown in Figure 4,
the Recommended Circuit
Schematic diagram, for the
transmitter and receiver sections.
These filter circuits suppress V
CC
noise of 50 mV peak-to-peak or
less over a broad frequency
range. This prevents receiver
sensitivity degradation as well as
false-lock or loss-of-lock in the
clock recovery circuitry due to
V
CC
noise. It is recommended
that surface-mount components
be used. Use tantalum capacitors
for the 10
μ
F capacitors and
monolithic, ceramic bypass
capacitors for the 0.1
μ
F
FILTER
PINS
R7
R6
R8
V
CC
C3
C4
L1
L2
C1
C2
R15
R1
R4
C5
R3
R2
V
CC
TERMINATE AT
FIBER-OPTIC
TRANSCEIVER
INPUTS
TERMINATE
AT THE
DEVICE
INPUTS
C8
R12
R10
R9
R14
C7
R11
R13
V
CC
CLK
CLK
R5
C6
1
REF CLK
2
LCK
3
CLK
4
CLK
5*
L
MON
6*
L
MON
T
XDIS
8*
NC
P
MON
18
17
RD
16
RD
15
SD
14
13
12
TD
11
TD
10
Rx
V
EE
Rx
V
CC
Tx
V
CC
Tx
V
EE
TERMINATE
AT CLOCK
INPUTS
REF
CLK
HFCT-5202
TOP VIEW
NO INTERNAL
CONNECTION
NO INTERNAL
CONNECTION
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE PECL SIGNALS.
R1 = R4 = R6 = R8 = R10 = R12 = R14 = 130
.
R2 = R3 = R5 = R7 = R9 = R11 = R13 = 82
.
C1 = C2 = C3 = C5 = C6 = C7 = 0.1 μF.
C4 = C8 = 10 μF.
L1 = L2 = 1 μH COIL.
R15 = 10 k
.
FOR THE SINGLE MODE HFCT-5202 TRANSCEIVER, PINS 5 - 9 ARE USED FOR LASER DIODE BIAS
AND OPTICAL POWER MONITORING AS WELL AS TO PROVIDE A TRANSMITTER DISABLE
FUNCTION. *FOR THE MULTIMODE HFBR-5207 TRANSCEIVER, PINS 5 - 9 ARE NOT USED.
OPTIONAL
RD
RD
SD
VCC
TD
TD
Rx
Tx
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