
3
For input optical power greater
than the specified receiver
sensitivity of -28 dBm, the bit-
error-ratio will be better than
1 x 10
-10
. As the input power is
decreased by several dB, the bit-
error-ratio degrades. Within 1 dB
below the 1 x 10
-2
BER input
optical power level, the CDR will
begin to lose lock and the clock
frequency will drift from 155.52
MHz. Once the CDR loses lock,
the clock frequency will sweep
through the entire VCO range,
about 140 to 200 MHz. The rate
of the sweep is inversely propor-
tional to the input optical power
and will reach its maximum at a
point of 2 dB below the lock
point. Since data is retimed to the
clock, a loss of lock will produce
an output data stream consisting
of randomly switching data bits,
i.e., noise.
Receiver Signal Detect
As the input optical power is
decreased, Signal Detect will
switch from high to low (de-
assert point) at a point between
3 dB below minimum guaranteed
sensitivity and the no light input
level. As the input optical power
is increased from very low levels,
Signal Detect will switch back
from low to high (assert point).
The assert level will be at least
0.5 dB higher than the de-assert
level. This single-ended low-
power PECL output is designed
to drive a standard PECL input
using a 10 k
load instead of the
normal 50
PECL load.
Reference Clock
In applications where the receiver
recovered clock frequency is not
allowed to drift upon loss of input
optical signal, the HFCT-5202
has the ability to generate a local
clock output by multiplying an
optional, external 19.44 MHz
reference clock up to the
OC-3/STM1 155.52 MHz rate.
This feature is possible because
the clock recovery system
consists of two loops: a data loop
which locks onto the incoming
optical data stream, and a second
reference loop which locks onto
the optional external reference
clock.
This optional feature is initiated
by applying a Lock-to-Reference
logic signal to pin 2 (Lck Ref-)
which switches the loop to the
external reference clock and
disables the received data
outputs. Pin 2 (Lck Ref-) can be
driven from the Signal Detect pin
15 (SD) output or from other
logic further upstream in the
ATM interface which may be
monitoring the quality of the
received data stream.
Transceiver Specified for
Wide Temperature Range
Operation
The HFCT-5202 is specified for
operation over normal commer-
cial temperature range of 0
°
to
+70
°
C (HFCT-5202B/D) or the
extended temperature range of
–40
°
C to +85
°
C (HFCT-5202A/C).
Other Members of HP
155 Mb/s Product Family
HFCT-5205, 1300 nm laser-
based 1 x 9 SC receptacle
transceiver for 15 km links with
SMF cables (without CDR)
HFBR-5208 1300 nm LED
based 1 x 9 SC receptacle
transceiver for 500 m links with
MMF cables (drop in
replacement for HFCT-5205)
XMT5370-155 1300 nm laser-
based transmitter in pigtailed
package for 15 km links with
SMF cables
XMT5170-155 1300 nm laser-
based transmitter in pigtailed
package for 40 km links with
SMF cables
RCV1201D-155 receiver in
pigtailed package for 15 km
and 40 km links with SMF
cables
RGR1551 receiver with integral
clock and data recovery in
pigtailed packages for 15 km
Applications Information
Typical BER Performance of
Receiver versus Input Optical
Power Level
The HFCT-5202 transceiver can
be operated at Bit-Error-Rate
conditions other than the
required BER = 1 x 10
-10
of the
ATM Forum 155.52 Mb/s Physical
Layer Standard. The typical
tradeoff of BER versus Relative
Input Optical Power is shown in
Figure 3. The Relative Input
Optical Power in dB is referenced
to the Input Optical Power
parameter value in the Receiver
Optical Characteristics table. For
Figure 3. Relative Input Optical
Power–dBm Avg.
B
-5
3
10
-2
RELATIVE INPUT OPTICAL POWER – dBm avg.
-3
1
-2
0
10
-4
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-14
10
-15
10
-5
10
-3
-4
-1
2
LINEAR EXTRAPOLATION
OF 10
-4
THROUGH 10
-7
DATA POINTS
ACTUAL DATA
POINTS