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參數(shù)資料
| 型號： | HFCT-5202 |
| 英文描述： | 155 Mb/s Single Mode Fiber Transceiver with Integrated Clock and Data Recovery for ATM, SONET OC-3/SDH STM-1(應(yīng)用于ATM, SONET OC-3/SDH STM-1帶集成時鐘和數(shù)據(jù)恢復(fù)的155 Mb/s單模式光收發(fā)器) |
| 中文描述： | 155 Mb / s的對ATM，SONET的OC-3/SDH的STM - 1單模光纖收發(fā)器（應(yīng)用于自動取款機(jī)，SONET的OC-3/SDH的STM - 1帶集成時鐘和數(shù)據(jù)恢復(fù)的155 MB的集成的時鐘和數(shù)據(jù)恢復(fù)/擰單模式光收發(fā)器） |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 170K |
| 代理商： | HFCT-5202 |
2
Figure 1. Block Diagram.
Figure 2. Relative Timing Relationship between Output Retimed Data and
Recovered Clock Signals.
to generate a local timing signal
from an external, low-frequency
reference clock. The external
timing signal acts as the
reference clock when incoming
optical signals become
undetectable.
Transmitter Section
The transmitter section of the
HFCT-5202 is similar to other
Hewlett-Packard 1300 nm single
mode transceivers in use at the
155 Mb/s data rate. It consists of
a 1300 nm InGaAsP laser in an
eye-safe optical subassembly
(OSA) which mates to the fiber
cable. The laser OSA is driven by
a custom, silicon bipolar IC
which converts differential input
PECL logic signal into an analog
laser drive current.
Receiver Section
The receiver section of the
transceiver provides a full set of
features including an integral
clock and data recovery (CDR)
circuit together with an optional,
selectable receiver local clock
source.
The receiver utilizes an InGaAs
PIN photodiode mounted
together with a transimpedance
preamplifier IC in an OSA. This
OSA is connected to a custom,
silicon bipolar circuit providing
post-amplification and quantiza-
tion, CDR function, and optical
signal detection.
CDR Function
In normal operation, the CDR
data loop is able to acquire and
maintain bit lock without the use
of the optional, external refer-
ence clock. This loop consists of
a patented phase/frequency
detector with false-lock protec-
tion. The recovered clock is used
to retime the quantizer data
output, which completes the full
CDR function.
The relative timing relationship
between the output retimed data
and the recovered clock signals is
shown graphically in Figure 2.
SIGNAL DETECT
ELECTRICAL SUBASSEMBLY
CLOCK & DATA
RECOVERY
AND POST
AMPLIFIER IC
LASER
DRIVER
IC
TOP VIEW
PIN PHOTODIODE
DUPLEX SC
RECEPTACLE
LASER
PRE-
AMPLIFIER
IC
RETIMED DATA 2
DATA 2
OPTICAL
SUB-
ASSEMBLIES
RECOVERED CLOCK 2
REFERENCE CLOCK
LOCK-TO-REFERENCE
LASER BIAS MONITOR
POWER
MONITOR
TRANSMIT
DISABLE
BAUD INTERVAL
RD
RD
CLK
CLK
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
CLOCK PERIOD
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