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參數(shù)資料
| 型號： | HI-7153 |
| 廠商： | Intersil Corporation |
| 英文描述： | 128 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8通道，10位高速采樣A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HI-7153 |
13
HI-7153
The input voltage is first converted into a 5 bit result (plus
Out of Range information) by the flash converter. This flash
converter consists of an array of 33 auto-zeroed
comparators which perform a comparison between the input
voltage and subdivisions of the reference voltage. These
subdivisions of the reference voltage are formed by forcing
the reference voltage and its negative on the two ends of a
string of 32 resistors.
The 5 bit result of the first flash conversion is latched into the
upper five bits of double buffered latches. It is also converted
back into an analog signal by choosing the ladder voltage
which is closest to but less than the input voltage. The
selected voltage (VTAP) is then subtracted from the input
voltage. The residual is then amplified by a factor of 32 and
referenced to the negative reference voltage (VSCA =
32(VIN - VTAP) + V
REF-
). This subtraction and amplification
operation is performed by a Switched Capacitor amplifier
(SCA). The output of the SCA amplifier is between the
positive and negative reference voltages and can therefore
be digitized by the original 5 bit flash converter (second flash
conversion).
The 5 bit result of the second flash conversion is latched into
the lower five bits of double buffered latches. At the end of a
conversion, 10 bits of data plus an Out of Range bit are
latched into the second level of latches and can then be put
on the digital output pins.
The conversion takes place in three clock cycles and is
illustrated in Figure 2. When the conversion begins, the track
and hold goes into its hold mode for 1 clock cycle. During the
first half clock cycle the comparator array is in its auto-zero
mode and it samples the input voltage. During the second
half clock cycle, the comparators make a comparison
between the input voltage and the ladder voltages. At the
beginning of the third half clock cycle, the first most
significant 5 bit result becomes available. During the first
clock cycle, the SCA was sampling the input voltage. After
the first flash result becomes available and a ladder tap
voltage has been selected the SCA amplifies the residue
between the input and ladder tap voltages. During the next
three half clock cycles, while the SCA output is settling to its
required accuracy, the comparators go into their auto-zero
mode and sample this voltage. During the sixth half clock
cycle, the comparators perform another comparison whose
5 bit result becomes available on the next clock edge.
Reference Input
The reference input to the HI-7153 is buffered by a high
speed CMOS amplifier. The reference input range is 2.2V to
2.6V. The reference input voltage should be applied follow-
ing the application of V+ and V- supplies.
FIGURE 1. DETAILED BLOCK DIAGRAM
5 TO 32
DECODER
OVR
D9
DATA
OUTPUTS
D0
BUS
HBE
HOLD
RD
WR
CS
SMODE
CLK
EOC
L
O
BUS
CTRL
3
A
CONTROL
LOGIC
LATCH
AZ
33
AZ
LATCH
AZ
32
AZ
LATCH
AZ
1
AZ
LATCH
AZ
2
AZ
AZ
AZ
AZ
(-V
REF
)
V
REF
AG
A
IN0
A
IN1
A
IN2
A
IN3
A
IN4
A
IN5
A
IN6
A
IN7
(+V
REF
)
R
-
+
-
+
(AG)
R
REF (+)
AMP
REF (-)
AMP
SCAZ
SCAZ
SCAZ
-
+
-
+
32C
C
SCAZ
SCAZ
(-V
REF
)
-
+
HOLD
(AG)
HOLD
AMP
SWITCHED
CAP. AMP
C
H
TRACK
BUFFER
AMP
POWER SUPPLY
DISTRIBUTION
V+
V-
GND
DG
MUX DECODER
LATCHES
TEST
ALE
A0
A1
A2
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