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參數(shù)資料
| 型號(hào)： | HI-7153 |
| 廠商： | Intersil Corporation |
| 英文描述： | 128 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8通道，10位高速采樣A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 977K |
| 代理商： | HI-7153 |
14
HI-7153
Analog Multiplexer
The multiplexer channel assignments are shown in Table 1
and can be randomly addressed. Address inputs A0 - A2 are
binary coded and are TTL/CMOS compatible. During power
up the circuit is initialized and multiplexer channel A
IN0
is
selected. The multiplexer address is transparent when ALE
is high and CS is low. The address data is latched on the
falling edge of the ALE signal. The multiplexer channel
acquisition timing (Timing Diagrams, Slow Memory Mode)
occurs approximately 500ns after the rising edge of HOLD.
The multiplexer features a typical break-before-make switch
action of 44ns.
Track And Hold
A Track and Hold amplifier has been fully integrated on the
front end of the A/D converter. Because of the sampling
nature of this A/D converter, the input is required to stay
constant only during the first clock cycle. Therefore, the
Track and Hold (T/H) amplifier ‘‘holds’’ the input voltage only
during the first clock cycle and it acquires the input voltage
for the next conversion during the remaining two clock
cycles. The high input impedance of the T/H input amplifier
simplifies analog interfacing. Input signals up to
±
V
REF
can
be directly connected to the A/D without buffering. The T/H
amplifier typically settles to within
1
/
4
LSB in 1.5
μ
s. The A/D
output code table is presented in Table 2.
The timing signals for the Track and Hold amplifier are
generated internally, and are also provided externally
(HOLD) for synchronization purposes.
All of the internal amplifiers are offset trimmed during
manufacturing to give improved accuracy and to minimize
the number of external components. If necessary, offset
error can be adjusted by using digital post correction.
TABLE 1. MULTIPLEXER CHANNEL SELECTION
ADDRESS AND CONTROL INPUTS
ANALOG
CHANNEL
SELECTED
A2
A1
A0
CS
ALE
0
0
0
0
1
A
IN0
0
0
1
0
1
A
IN1
0
1
0
0
1
A
IN2
0
1
1
0
1
A
IN3
1
0
0
0
1
A
IN4
1
0
1
0
1
A
IN5
1
1
0
0
1
A
IN6
1
1
1
0
1
A
IN7
TABLE 2. A/D OUTPUT CODE TABLE
ANALOG INPUT*
OUTPUT DATA (2’S COMPLEMENT)
LSB = 2(V
REF
)/1024
≥
+V
REF
V
REF
= 2.500V
OVR
MSB
9
8
7
6
5
4
3
2
1
LSB 0
2.500 to V+ (+OVR)
1
0
0
0
0
0
0
0
0
0
0
+V
REF
- 1LSB
2.49512 (+Full Scale)
0
0
1
1
1
1
1
1
1
1
1
+1LSB
0.00488
0
0
0
0
0
0
0
0
0
0
1
0
0.000
0
0
0
0
0
0
0
0
0
0
0
-1LSB
-0.00488
0
1
1
1
1
1
1
1
1
1
1
-V
REF
≤
-V
REF
- 1LSB
-2.500 (-Full Scale)
0
1
0
0
0
0
0
0
0
0
0
2.50488 to V- (-OVR)
1
1
0
0
0
0
0
0
0
0
0
* The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage.
FIGURE 2. INTERNAL ADC TIMING DIAGRAM
N CONVERSION
N+1 CONVERSION
1
2
3
4
5
6
HOLD V
IN
(N)
HOLD V
IN
(N+1)
TRACK V
IN
(N+1)
SAMPLE
V
IN
(N)
SAMPLE
V
IN
(N+1)
SAMPLE RESIDUAL
CONVERT
UPPER
5 BITS
CONVERT
LOWER
5 BITS
AMPLIFY RESIDUAL
SAMPLE V
IN
(N)
SAMPLE V
IN
(N+1)
V
IN
(N) DATA
CLOCK
TRACK AND HOLD
COMPARATOR
AUTO-ZERO (AZ)
SCA AUTO-ZERO
(SCAZ)
INTERNAL DATA
10 BITS + OVR
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