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參數(shù)資料
| 型號(hào)： | HI-7153 |
| 廠商： | Intersil Corporation |
| 英文描述： | 128 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 8通道，10位高速采樣A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大?。?/td> | 977K |
| 代理商： | HI-7153 |
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HI-7153
presented in Table 5 for the DMA mode of operation.
Optimizing System Performance
The HI-7153 has three ground pins (AG, DG, GND) for
improved system accuracy. Proper grounding and bypassing
is illustrated in Figure 3. The AG pin is a ground pin and is
used internally as a reference ground. The reference input
and analog input should be referenced to the analog ground
(AG) pin. The digital inputs and outputs should be referenced
to the digital ground (DG) pin. The GND pin is a return point
for the supply current of the comparator array. The compara-
tor array is designed such that this current is approximately
constant at all times and does not vary with input voltage. By
virtue of the switched capacitor nature of the comparators, it is
necessary to hold GND firmly at zero volts at all times. There-
fore, the system ground star connection should be located as
close to this pin as possible.
As in any analog system, good supply bypassing is necessary
in order to achieve optimum system performance. The power
supplies should be bypassed with at least a 20
μ
F tantalum
and a 0.1
μ
F ceramic capacitor to GND. The reference input
should be bypassed with a 0.1
μ
F ceramic capacitor to AG.
The capacitor leads should be as short as possible.
The pins on the HI-7153 are arranged such that the analog
pins are well isolated from the digital pins. In spite of this
arrangement, there is always some pin-to-pin coupling.
Therefore the analog inputs to the device should not be
driven from very high output impedance sources. PC board
layout should screen the analog and reference inputs with
guard rings on both sides of the PC board, connected to AG.
TABLE 3. SLOW MEMORY MODE I/O TRUTH TABLE (SMODE = V+)
CS
WR
RD
BUS
HBE
ALE
FUNCTION
0
0
X
X
X
X
Initiates a conversion.
0
X
X
X
X
1
Selects mux channel. Address data is latched on falling edge of ALE. Latch
is transparent when ALE is high.
1
X
X
X
X
X
Disables all chip commands.
0
X
0
1
X
X
Enables D0 - D9 and OVR.
0
X
0
0
0
X
Low byte enable: D0 - D7
0
X
0
0
1
X
High byte enable: D8 - D9, OVR
X
X
1
X
X
X
Disables all outputs (high impedance).
X = Don’t Care
TABLE 4. FAST MEMORY MODE I/O TRUTH TABLE (SMODE = DG)
CS
WR
RD
BUS
HBE
ALE
FUNCTION
0
0
X
X
X
X
Continuous conversion, WR may be tied to DG.
0
X
X
X
X
1
Selects mux channel. Address data is latched on falling edge of ALE. Latch
is transparent when ALE is high.
1
X
X
X
X
X
Disables all chip commands.
0
X
0
1
X
X
Enables D0 - D9 and OVR.
0
X
0
0
0
X
Low byte enable: D0 - D7
0
X
0
0
1
X
High byte enable: D8 - D9, OVR
X
X
1
X
X
X
Disables all outputs (high impedance).
X = Don’t Care
TABLE 5. DMA MODE I/O TRUTH TABLE (SMODE = V+, CS = WR = RD = DG)
BUS
HBE
ALE
FUNCTION
X
X
1
Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high.
1
X
X
Enables D0 - D9 and OVR.
0
0
X
Low byte enable: D0 - D7
0
1
X
High byte enable: D8 - D9, OVR
X = Don’t Care
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