tDD Access Time from CE - 75 150 ns t
參數(shù)資料
型號: HI3-574AJN-5
廠商: Intersil
文件頁數(shù): 17/18頁
文件大小: 0K
描述: IC ADC 12BIT 40KSPS 28-PDIP
標(biāo)準(zhǔn)包裝: 13
位數(shù): 12
采樣率(每秒): 40k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 720mW
電壓電源: 雙 ±
工作溫度: 0°C ~ 75°C
安裝類型: 通孔
封裝/外殼: 28-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 28-PDIP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,單極;2 個單端,雙極
8
FN3096.6
August 7, 2008
READ MODE
tDD
Access Time from CE
-
75
150
ns
tHD
Data Valid After CE Low
25
-
ns
tHL
Output Float Delay
-
100
150
ns
tSSR
CS to CE Setup
50
-
ns
tSRR
R/C to CE Setup
0
-
ns
tSAR
AO to CE Setup
50
-
ns
tHSR
CS Valid After CE Low
0
-
ns
tHRR
R/C High After CE Low
0
-
ns
tHAR
AO Valid After CE Low
50
-
ns
tHS
STS Delay After Data Valid
300
-
1200
ns
Timing Specifications (HI-674A) +25°C, Note 5, Unless Otherwise Specified.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
tDSC
STS Delay from CE
-
200
ns
tHEC
CE Pulse Width
50
-
ns
tSSC
CS to CE Setup
50
-
ns
tHSC
CS Low During CE High
50
-
ns
tSRC
R/C to CE Setup
50
-
ns
tHRC
R/C Low During CE High
50
-
ns
tSAC
AO to CE Setup
0
-
ns
tHAC
AO Valid During CE High
50
-
ns
tC
Conversion Time
12-Bit Cycle TMIN to TMAX
812
15
s
8-Bit Cycle TMIN to TMAX
58
10
s
READ MODE
tDD
Access Time from CE
-
75
150
ns
tHD
Data Valid After CE Low
25
-
ns
tHL
Output Float Delay
-
100
150
ns
tSSR
CS to CE Setup
50
-
ns
tSRR
R/C to CE Setup
0
-
ns
tSAR
AO to CE Setup
50
-
ns
tHSR
CS Valid After CE Low
0
-
ns
tHRR
R/C High After CE Low
0
-
ns
tHAR
AO Valid After CE Low
50
-
ns
tHS
STS Delay After Data Valid
25
-
850
ns
NOTES:
5. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3k
Ω load.
6. For the “10V Input”, Pin 13.
7. For the “20V Input”, Pin 14.
Timing Specifications (HI-574A) +25°C, Note 5, Unless Otherwise Specified. (Continued)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
HI-574A, HI-674A
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