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參數(shù)資料
| 型號： | HI3-574AJN-5 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 40KSPS 28-PDIP |
| 標準包裝： | 13 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 720mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 75°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 供應商設備封裝： | 28-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極 |
9
FN3096.6
August 7, 2008
Definitions of Specifications
Linearity Error
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs 1/2 LSB (1.22mV for 10V span) before
the first code transition (all zeros to only the LSB “on”). “Full
scale” is defined as a level 11/2 LSB beyond the last code
transition (to all ones). The deviation of a code from the true
straight line is measured from the middle of each particular
code.
The HI-X74AK grade is guaranteed for maximum nonlinearity
of ±1/2 LSB. For this grade, this means that an analog value
which falls exactly in the center of a given code width will result
in the correct digital output code. Values nearer the upper or
lower transition of the code width may produce the next upper
or lower digital output code. The HI-X74AJ is guaranteed to
±1
LSB max error. For this grade, an analog value which falls
within a given code width will result in either the correct code for
that region or either adjacent one.
Note that the linearity error is not user-adjustable.
Differential Linearity Error (No Missing Codes)
A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every
code must have a finite width. For the HI-X74AK grade, which
guarantees no missing codes to 12-bit resolution, all 4096
codes must be present over the entire operating temperature
ranges. The HI-X74AJ grade guarantees no missing codes to
11-bit resolution over temperature; this means that all code
combinations of the upper 11 bits must be present; in practice
very few of the 12-bit codes are missing.
Unipolar Offset
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset
temperature coefficient specifies the maximum change of the
transition point over temperature, with or without external
adjustment.
Bipolar Offset
Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value 1/2 LSB below analog common. The bipolar
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over
temperature.
Full Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 11/2 LSB below the
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.
Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1VLOGIC
Logic supply pin (+5V)
2
12/8
Data Mode Select - Selects between
12-bit and 8-bit output modes.
3CS
Chip Select - Chip Select high disables
the device.
4AO
Byte Address/Short Cycle - See Table 3
for operation.
5R/C
Read/Convert - See Table 3 for operation.
6
CE
Chip Enable - Chip Enable low disables
the device.
7VCC
Positive Supply (+12V/+15V)
8
REF OUT
+10V Reference
9
AC
Analog Common
10
REF IN
Reference Input
11
VEE
Negative Supply (-12V/-15V).
12
BIP OFF
Bipolar Offset
13
10V Input
10V Input - Used for 0V to 10V and -5V to
+5V input ranges.
14
20V Input
20V Input - Used for 0V to 20V and -10V to
+10V input ranges.
15
DC
Digital Common
16
DB0
Data Bit 0 (LSB)
17
DB1
Data Bit 1
18
DB2
Data Bit 2
19
DB3
Data Bit 3
20
DB4
Data Bit 4
21
DB5
Data Bit 5
22
DB6
Data Bit 6
23
DB7
Data Bit 7
24
DB8
Data Bit 8
25
DB9
Data Bit 9
26
DB10
Data Bit 10
27
DB11
Data Bit 11 (MSB)
28
STS
Status Bit - Status high implies a conversion
is in progress.
HI-574A, HI-674A
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參數(shù)描述 |
|---|---|
| HI3-574AJN-5Z | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC W/ANNEAL ADC 12BIT 5 0KSPS COM RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI3-574AKN-5 | 功能描述:IC ADC 12BIT 40KSPS 28-PDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| HI3-574AKN-5Z | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC W/ANNEAL ADC 12BIT 5 0KSPS COM RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| HI3-574ALN-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HI-3582 | 制造商:HOLTIC 制造商全稱:Holt Integrated Circuits 功能描述:3.3V ARINC 429 TERMINAL IC |
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