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參數(shù)資料
| 型號(hào)： | HI3197JCQ |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | DAC |
| 英文描述： | 10-Bit, 125 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48 |
| 文件頁(yè)數(shù)： | 3/25頁(yè) |
| 文件大小： | 284K |
| 代理商： | HI3197JCQ |
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3
Pin Descriptions and I/O Pin Equivalent Circuits
PIN NO
SYMBOL
I/O
TYPICAL
VOLTAGE
LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
1 to 6
45 to 48
DA0 to DA9
I
TTL
Side A Data Input.
7 to 16
DB0 to DA9
I
TTL
Side B Data Input.
17
DIV2IN
I
TTL
1
/
2
Frequency-Divided Clock Input.
Use this pin for MUX.1A or MUX.2
mode. Leave open for other modes.
18
DIV2OUT
O
TTL
1
/
2
Frequency-Divided Clock Out-
put. The signal with the
1
/
2
fre-
quency divided clock (DIV2OUT) is
output for MUX.1A mode. Leave
open for other modes.
19
CLK/T
I
TTL
Clock Input. Use this pin when the
clock is input in the TTL level. At
this time, leave Pins 20 and 21
open.
20
CLKP/E
I
PECL
Clock Input. Use this pin when the
clock is input in PECL level. At this
time, leave Pin 19 open.
21
CLKN/E
I
PECL
CLKP/E
When left open, this pin goes to
the threshold potential. Operation
is possible only with CLKP/E, but
complementary input is recom-
mended to attain fast and stable
operation.
Complementary
Input.
6
48
16
1
45
7
TO
DGND1
V
REF
TO
TO
DV
CC1
17
DGND1
V
REF
DV
CC1
18
DGND1
DV
CC1
19
DGND1
V
REF
DV
CC1
20
DGND1
DV
CC1
21
HI3197
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