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參數(shù)資料
| 型號(hào)： | HI3197JCQ |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 125 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, PQFP48 |
| 文件頁(yè)數(shù)： | 4/25頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | HI3197JCQ |
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4
22
RESET/T
I
TTL
Reset signal input. When the multi-
ple HI3197 are operated at a time
for MUX.1A or MUX.1B mode, the
start timing of the internal
1
/
2
fre-
quency divider circuits should be
matched.
At this time, the reset signal is
used; when the reset signal is the
TTL level, Pin 22 is used and Pins
23 and 24 are left open. When the
reset signal is the PECL level, Pins
23 and 24 are used and Pin 22 is
left open. For the PECL level, oper-
ation is possible only with RE-
SETP/E as with the case for the
clock. The reset signal polarity can
be set by Pin 39 (RPOLARITY).
Leave the reset pin open when the
other modes are used.
23
RESETP/E
I
PECL
24
RESETN/E
I
PECL
25
DGND2
Single Power
Supply: GND Dual
Power Supplies:
-5V
Digital Power Supply.
26
C1
I
TTL
Function setting.
27
C2
I
TTL
28
C3
I
TTL
29
DV
CC2
Single Power
Supply: +5V Dual
Power Supplies:
GND
Digital Power Supply.
30
AV
CC0
OUTN
Analog Output Power Supply.
31
O
AV
CC0
- V
FS
D/A Negative Output. The inversion
of the D/A positive output pin is out-
put. Terminate the inversion without
pin with 50
when the inversion out-
put is not used and the positive out-
put is terminated with 50
.
32
AOUTP
O
AV
CC0
- V
FS
D/A positive output.
33
AGND2
Single Power
Supply: GND
Dual Power
Supplies: -5V
Analog Ground.
Pin Descriptions and I/O Pin Equivalent Circuits
(Continued)
PIN NO
SYMBOL
I/O
TYPICAL
VOLTAGE
LEVEL
EQUIVALENT CIRCUIT
DESCRIPTION
22
DGND1
DV
CC1
V
REF
23
DGND1
DV
CC1
24
27
DGND1
V
REF
DV
CC1
26
28
31
AGND2
32
AV
CC0
RO
RO
HI3197
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