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參數資料
| 型號： | HM1-6504B883 |
| 廠商： | Intersil Corporation |
| 英文描述： | 4096 x 1 CMOS RAM |
| 中文描述： | 4096 × 1 CMOS存儲器 |
| 文件頁數： | 4/10頁 |
| 文件大小： | 167K |
| 代理商： | HM1-6504B883 |
6-137
TABLE 2. HM-6504/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER
SYMBOL
(NOTES 1, 2)
CONDITIONS
GROUP
A SUB-
GROUPS
TEMPERA-
TURE
LIMITS
UNITS
HM-6504S/883
HM-6504B/883
HM-6504/883
MIN
MAX
MIN
MAX
MIN
MAX
Chip Enable
Access Time
(1)
TELQV
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-
120
-
200
-
300
ns
Address Access
Time
(2)
TAVQV
VCC = 4.5 and
5.5V, Note 3
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
-
120
-
220
-
320
ns
Chip Enable
Pulse Negative
Width
(5)
TELEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
120
-
200
-
300
-
ns
Chip Enable
Pulse Positive
Width
(6)
TEHEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
50
-
90
-
120
-
ns
Address Setup
Time
(7)
TAVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
-
20
-
20
-
ns
Address Hold
Time
(8)
TELAX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
40
-
50
-
50
-
ns
Write Enable
Pulse Width
(9)
TWLWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
20
-
60
-
80
-
ns
Write Enable
Pulse Setup
Time
(10)
TWLEH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
70
-
150
-
200
-
ns
Early Write Pulse
Setup Time
(11)
TWLEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
-
0
-
0
-
ns
Early Write Pulse
Hold Time
(13)
TELWH
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
40
-
60
-
80
-
ns
Data Setup Time
(14)
TDVWL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
-
0
-
0
-
ns
Early Write Data
Setup Time
(15)
TDVEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
0
-
0
-
0
-
ns
Data Hold Time
(16)
TWLDX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
25
-
60
-
80
-
ns
Early Write Data
Hold Time
(17)
TELDX
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
25
-
60
-
80
-
ns
Read or Write
Cycle Time
(18)
TELEL
VCC = 4.5 and
5.5V
9, 10, 11
-55
o
C
≤
T
A
≤
+125
o
C
170
-
290
-
420
-
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
HM-6504/883
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