6-220
March 1997
HM-65642/883
8K x 8 Asynchronous
CMOS Static RAM
Features
This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
Full CMOS Design
Six Transistor Memory Cell
Low Standby Supply Current . . . . . . . . . . . . . . . .100
μ
A
Low Operating Supply Current. . . . . . . . . . . . . . . 20mA
Fast Address Access Time . . . . . . . . . . . . . . . . . .150ns
Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V
CMOS/TTL Compatible Inputs/Outputs
JEDEC Approved Pinout
Equal Cycle and Access Times
No Clocks or Strobes Required
Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
Temperature Range -55
o
C to +125
o
C
Easy Microprocessor Interfacing
Dual Chip Enable Control
Description
The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu-
lar, interfacing with the Intersil 80C86 and 80C88 micropro-
cessors is simplified by the convenient output enable (G)
input.
The HM-65642/883 is a full CMOS RAM which utilizes an
array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili-
tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices
Ordering Information
PACKAGE
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
150ns/75
μ
A
150ns/150
μ
A
200ns/250
μ
A
PKG. NO.
CERDIP
HM1-65642B/883
HM1-65642/883
HM1-65642C/883
F28.6
CLCC
HM4-65642B/883
HM4-65642/883
-
J32.A
Pinouts
HM-65642/883 (CERDIP)
TOP VIEW
HM4-65642/883 (CLCC)
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
E2
A8
A9
A11
A10
DQ7
DQ6
DQ5
DQ4
DQ3
W
G
E1
5
6
7
8
11
10
9
13
12
27
28
29
26
25
24
23
22
21
3
2
1
4
32
31
30
16
17
18
19
20
14
15
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
D
D
G
N
D
D
D
V
N
N
A
A
E
W
A8
A9
A11
G
A10
E1
DQ7
DQ6
NC
PIN
DESCRIPTION
A
Address Input
DQ
Data Input/Output
E1
Chip Enable
E2
Chip Enable
W
Write Enable
G
Output Enable
NC
No Connections
GND
Ground
VCC
Power
File Number
3004.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil Corporation 1999