參數(shù)資料
型號: HM1-65642883
廠商: Intersil Corporation
英文描述: 8K x 8 Asynchronous CMOS Static RAM
中文描述: 8K的× 8異步的CMOS靜態(tài)RAM
文件頁數(shù): 6/9頁
文件大小: 77K
代理商: HM1-65642883
6-225
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data Retention voltage and supply current are guaran-
teed over the operating temperature range. The following
rules ensure data retention:
1. The RAM must be kept disabled during data retention. This is ac-
complished by holding the E2 pin between -0.3V and GND.
2. During power-up and power-down transitions, E2 must be held
between -0.3V and 10% of VCC.
3. The RAM can begin operating one TAVAX after VCC reaches the
minimum operating voltage of 4.5V.
Read Cycles
FIGURE 2. READ CYCLE I: W, E2 HIGH; G, E1 LOW
FIGURE 3. READ CYCLE II: W HIGH
4.5V
VIH
VCC
E2
VCCOR
GND
DATA RETENTION MODE
TAVAX
FIGURE 1. DATA RETENTION
A
ADDRESS 1
Q
TAVAX
TAVQV
TAXQX
ADDRESS 2
DATA 1
DATA 2
TAVAX
TAVQV
TE1LQV
TE1LQX
TE1HQZ
TE2LQZ
TE2HQV
TE2HQX
TGLQV
TGLQX
TGHQZ
A
E2
G
Q
E1
HM-65642/883
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