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參數(shù)資料
| 型號： | HM5117405S-5 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 4 EDO DRAM, 50 ns, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOJ-26/24 |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 346K |
| 代理商： | HM5117405S-5 |
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HM5116405 Series, HM5117405 Series
16
To get out of test mode and enter a normal operation mode, perform either a regular
CAS-
before-
RAS refresh cycle or RAS-only refresh cycle.
20. In a test mode read cycle, the value of t
RAC, t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
21. t
HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of
CAS cycle (t
CAS + tCP + 2 tT) becomes greater
than the specified t
HPC (min) value.
The value of
CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later risting edge of
RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS between t
OHR and tOH , and between tOFR and t OFF.
22. Data output turns off and becomes high impedance from later rising edge of
RAS and CAS .
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS between t
OHR and tOH and between tOFR and t OFF.
23. XXX: H or L (H: V
IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH or VIL.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5117405S-6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:16M EDO DRAM (4-MWORD X 4-BIT) 4K REFRESH / 2K REFRESH |
| HM5117405S-7 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:16 M EDO DRAM (4-Mword ′ 4-bit) 4 k Refresh/2 k Refresh |
| HM5117405TS-5 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:16M EDO DRAM (4-MWORD X 4-BIT) 4K REFRESH / 2K REFRESH |
| HM5117405TS-6 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:16M EDO DRAM (4-MWORD X 4-BIT) 4K REFRESH / 2K REFRESH |
| HM5117405TS-7 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:16M EDO DRAM (4-MWORD X 4-BIT) 4K REFRESH / 2K REFRESH |
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