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參數(shù)資料
| 型號： | HM5264805FTT-A60 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| 中文描述： | 6400 LVTTL接口SDRAM的133 MHz/100 MHz的 |
| 文件頁數(shù)： | 11/67頁 |
| 文件大?。?/td> | 870K |
| 代理商： | HM5264805FTT-A60 |
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HM5264165F/HM5264805F/HM5264405F-75/A60/B60
11
Column address strobe and read command [READ]:
This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY7; HM5264165F, AY0 to
AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select address (BS). After the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READ A]:
This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
Column address strobe and write command [WRIT]:
This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F,
AY0 to AY9; HM5264405F) and the bank select address (A12/A13) become the burst write start address.
When the single write mode is selected, data is only written to the location specified by the column address
(AY0 to AY7; HM5264165F, AY0 to AY8; HM5264805F, AY0 to AY9; HM5264405F) and the bank select
address (A12/A13).
Write with auto-precharge [WRIT A]:
This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page,
this command is illegal.
Row address strobe and bank activate [ACTV]:
This command activates the bank that is selected by
A12/A13 (BS) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank
2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]:
This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If
A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]:
This command starts a precharge operation for all banks.
Refresh [REF/SELF]:
This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]:
The SDRAM has a mode register that defines how it operates. The mode register
is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the mode
register configuration. After power on, the contents of the mode register are undefined, execute the mode
register set command to set up the mode register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264405FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FLTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264805FTT-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805LTT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805LTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805LTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805TT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
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