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參數(shù)資料
| 型號(hào)： | HM5264805FTT-A60 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| 中文描述： | 6400 LVTTL接口SDRAM的133 MHz/100 MHz的 |
| 文件頁數(shù)： | 17/67頁 |
| 文件大?。?/td> | 870K |
| 代理商： | HM5264805FTT-A60 |
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HM5264165F/HM5264805F/HM5264405F-75/A60/B60
17
From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]:
When these commands are executed, the SDRAM enters the IDLE state after
t
RP
has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The SDRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]:
These commands result in no operation.
To [READ], [READ A]:
A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]:
A write operation starts. (However, an interval of t
RCD
is required.)
To [ACTV]:
This command makes the other bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands set the SDRAM to precharge mode. (However, an interval of t
RAS
is
required.)
From READ state, command operation
To [DESL], [NOP]:
These commands continue read operations until the burst operation is completed.
To [BST]:
This command stops a full-page burst.
To [READ], [READ A]:
Data output by the previous read command continues to be output. After
CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]:
These commands stop a burst read, and start a write cycle.
To [ACTV]:
This command makes other banks bank active. (However, an interval of t
RRD
is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]:
These commands stop a burst read, and the SDRAM enters precharge mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5264405FTT-A60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264165FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264405FTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805FLTT-B60 | 64M LVTTL interface SDRAM 133 MHz/100 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5264805FTT-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:64M LVTTL interface SDRAM 133 MHz/100 MHz |
| HM5264805LTT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805LTT-80 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805LTT-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
| HM5264805TT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SDRAM |
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