參數(shù)資料
型號(hào)： HM5425161B
廠商： Elpida Memory, Inc.
英文描述： 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
中文描述： 256M SSTL_2 DDR SDRAM的接口143 MHz/133 MHz/125 MHz/100 MHz的4 Mword】16位】4-bank/8-Mword】8位】4銀行/ 16 Mword】4位】4 -銀行
文件頁(yè)數(shù)： 24/65頁(yè)
文件大?。?/td> 489K
代理商： HM5425161B
HM5425161B, HM5425801B, HM5425401B Series
Data Sheet E0086H20
24
Read/Write Operations
Bank active:
A read or a write operation begins with the bank active command [ACTV]. The bank active
command determines a bank address (BA0, BA1) and a row address (AX0 to AX12). For the bank and the
row, a read or a write command can be issued t
RCD
after the ACTV is issued.
Read operation:
The burst length (BL), the
CAS
latency (CL) and the burst type (BT) of the mode register
are referred when a read command is issued. The burst length (BL) determines the length of a sequential
output data by the read command which can be set to 2, 4, or 8. The starting address of the burst read is
defined by the column address (AY0 to AY8; the HM5425161B, AY0 to AY9; the HM5425801B, AY0 to
AY9, AY11; the HM5425401B), the bank select address (BA0, BA1) which are loaded via the A0 to A12 and
BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by
CL (2 or 2.5) and t
AC
. The read burst start CL
t
CK
+ t
AC
(ns) after the clock rising edge where the read
command are latched. The DDR SDRAM output the data strobe through DQS or DQSU/DQSL
simultaneously with data. t
RPRE
prior to the first rising edge of the data strobe, the DQS or the DQSU/DQSL
are driven Low from V
TT
level. This low period of DQS is referred as read preamble. The burst data are
output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in
the next cycle after the burst read operation completed. t
RPST
from the last falling edge of the data strobe, the
DQS pins become High-Z. This low period of DQS is referred as read postamble.
Read Operation
(Burst Length)
D0
D1
D0
D1
D2
D3
D0
D1
D2
D3
D4
D5
D6
D7
CLK
CLK
Address
DQS*
Dout
BL = 2
BL = 4
BL = 8
Command
CAS
latency = 2
BL: Burst length
t1
t0
t2
t3
t4
t5
t6
t7
t8
t
RCD
t
RPRE
DQS*:DQS,DUSU/DQSL
t
RPST
ACTV
NOP
NOP
NOP
READ
Row
Column
相關(guān)PDF資料
PDF描述
HM5425401B 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425801B 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425161BTT-75A 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425801BTT-75A 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425401BTT-75A 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HM5425161B/801B/401B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 256M SSTL-2 Interface DDR SDRAM 143 MHz/133 MHz/125
HM5425161BTT-10 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425161BTT-75A 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425161BTT-75B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
HM5425401B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
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