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參數(shù)資料
| 型號： | HM5425401B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM) |
| 中文描述： | 256M DDR SDRAM的接口SSTL_2（256M SSTL_2接口的DDR同步DRAM）的 |
| 文件頁數(shù)： | 18/62頁 |
| 文件大?。?/td> | 1016K |
| 代理商： | HM5425401B |
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HM5425161B, HM5425801B, HM5425401B Series
18
Function Truth Table (4)
Current state
Write with auto-
pre-charge*
11
CS
RAS CAS WE
Address
Command
Operation
Next state
H
×
×
×
×
DESL
NOP
Precharging
L
H
H
H
×
×
NOP
NOP
Precharging
L
H
H
L
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
—
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
—
L
L
H
H
BA, RA
ACTV
ILLEGAL*
12
—
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
12
—
L
L
L
×
×
ILLEGAL
—
Notes: 1. H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
2. The DDR SDRAM is in "Precharging" state for t
RP
after precharge command is issued.
3. The DDR SDRAM reachs "IDLE" state t
RP
after precharge command is issued.
4. The DDR SDRAM is in "Refresh" state for t
RC
after auto-refresh command is issued.
5. The DDR SDRAM is in "Activating" state for t
RCD
after ACTV command is issued.
6. The DDR SDRAM is in "Active" state after "Activating" is completed.
7. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are
turned off.
8. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has
been output and DQ output circuits are turned off.
9. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
10.The DDR SDRAM is in "Write recovering" for t
WR
after the last data are input.
11.The DDR SDRAM is in "Write with auto-precharge" until t
WR
after the last data has been input.
12.This command may be issued for other banks, depending on the state of the banks.
13.All banks must be in "IDLE".
14.Before executing a write command to stop the preceding burst read operation, BST command must
be issued.
相關(guān)PDF資料 |
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| HM5425801B | 256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5425401BTT-10 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425401BTT-75A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425401BTT-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425801B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425801BTT-10 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
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