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參數(shù)資料
| 型號(hào)： | HMMC-5618 |
| 元件分類(lèi)： | 放大器 |
| 英文描述： | 6000 MHz - 20000 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER |
| 封裝： | 0.0326 X 0.0326 INCH, DIE |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | HMMC-5618 |
1
Description
The HMMC-5618 6–20 GHz
MMIC is an efficient two–stage
medium-power amplifier that is
designed to be used as a cascad-
able intermediate gain block for
EW applications. In communica-
tion systems, it can be used as
an amplifier for a local oscillator
or as a transmit amplifier. It is
fabricated using a PHEMT inte-
grated circuit structure that
provides exceptional efficiency
and flat gain performance. Dur-
ing typical operation, with a sin-
gle 5–volt DC power supply,
each gain stage is biased for
Class–A operation for optimal
power output with minimal dis-
tortion. The RF input and RF
output has matching circuitry
for use in 50 ohm environments.
The backside of the chip is both
RF and DC ground. This helps
simplify the assembly process
and reduces assembly related
performance variations and
costs.
Agilent HMMC-5618
6–20 GHz Medium Power
Amplifier
Data Sheet
Absolute Maximum Ratings[1]
1. Absolute maximum ratings for continuous operation unless otherwise noted.
Symbol
Parameters/Conditions
Min.
Max.
Units
VD1,VD2
Drain Supply Voltage
5.5
Volts
VG1
Optional Gate Supply Voltage
5
+1
Volts
VG2
Optional Gate Supply Voltage
10
+1
Volts
ID1
Drain Supply Current
70
mA
ID2
Drain Supply Current
84
mA
Pin
RF Input Power[2]
2. Operating at this power level for extended (continuous) periods is not recommended.
20
dBm
Tch
Channel Temperature[3]
3. Refer to DC Specifications/Physical Properties table for de–rating information.
160
°C
TA
Backside Ambient Temperature
55
+100
°C
Tst
Storage Temperature
65
+150
°C
Tmax
Max. Assembly Temperature
300
°C
Notes:
Features
High Efficiency:
11% @ P-1dB Typical
Output Power, P-1dB:
18 dBm Typical
High Gain:
14 dB Typical
Flat Gain Response:
± 0.5 dB Typical
Low Input/Output VSWR:
<1.7:1 Typical
Single Supply Bias:
5 volts (@ 115 mA typ.)
with Optional Gate Bias
Chip Size:
920 × 920 m (36.2 × 36.2 mils)
Chip Size Tolerance:
± 10 m (± 0.4 mils)
Chip Thickness:
127 ± 15 m (5.0 ± 0.6 mils)
Pad Dimensions:
80 × 80 m (3.2 × 3.2 mils)
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