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參數(shù)資料
| 型號： | HPC-DEV-SYS2 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance Communications MicroController |
| 中文描述： | 高性能通信微控制器 |
| 文件頁數(shù)： | 10/30頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HPC-DEV-SYS2 |
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Pin Descriptions
I/O PORTS
Port A is a 16-bit multiplexed address/data bus used for
accessing external program and data memory. Four associ-
ated bus control signals are available on port B. The Ad-
dress Latch Enable (ALE) signal is used to provide timing to
demultiplex the bus. Reading from and writing to external
memory are signalled by RD and WR respectively. External
memory can be addressed as either bytes or words with the
decoding controlled by two lines, Bus High Byte enable
(HBE) and Address/Data Line 0 (A0).
Port B is a 16-bit port, with 12 bits of bidirectional I/O. Pins
B10, B11, B12 and B15 are the control bus signals for the
address/data bus. Port B may also be configured via a func-
tion register BFUN to individually allow each bidirectional
I/O pin to have an alternate function.
B0:
TDX
UART Data Output
Closing Flag Output for HDLC
Y
1
Transmitter
B1:
CFLG1
B2:
CKX
UART Clock (Input or Output)
B3:
T2IO
Timer2 I/O Pin
B4:
T3IO
Timer3 I/O Pin
B5:
SO
MICROWIRE/PLUS Output
B6:
SK
MICROWIRE/PLUS Clock (Input or
Output)
B7:
HLDA
Hold Acknowledge Output
B8:
TS0
Timer Synchronous Output
B9:
TS1
Timer Synchronous Output
B10:
ALE
Address Latch Enable Output for
Address/Data Bus
B11:
WR
Address/Data Bus Write Output
B12:
HBE
High Byte Enable Output for Address/
Data Bus; also 8-Bit Mode Strap Input
on Reset.
B13:
TS2
Timer Synchronous Output
B14:
TS3
Timer Synchronous Output
B15:
RD
Address/Data Bus Read Output
When operating in the extended memory addressing mode,
four bits of port B can be used as followsD
B8:
BS0
Memory bank switch output 0 (LSB)
B9:
BS1
Memory bank switch output 1
B13:
BS2
Memory bank switch output 2
B14:
BS3
Memory bank switch output 3 (MSB)
Port I is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following func-
tions:
HLDC
Y
2 Clock Input
I0:
HCK2
I1:
NMI
Nonmaskable Interrupt Input
I2:
INT2
Maskable Interrupt/Input Capture
I3:
INT3
Maskable Interrupt/Input Capture
I4:
INT4/RDY Maskable Interrupt/Input Capture/
Ready Input
I5:
SI
MICROWIRE/PLUS Data Input
I6:
RDX
UART Data Input
HDLC
Y
1 Clock and Serial Decoder
Clock Input
I7:
HCK1
Port D is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following func-
tions:
REN1/FS/ Receiver
Y
1 Enable/Serial Decoder
RHCK1
Frame Sync Input/Receiver
Y
1 Clock
Input
Transmitter
Y
1 Enable Input
Receiver
Y
2 Enable Input/Receiver
RHCK2
Y
2 Clock Input
Transmitter
Y
2 Enable Input
Receiver
Y
1 Data Input
Transmitter
Y
1 Data Output
Receiver
Y
2 Data Input
Transmitter
Y
2 Data Output
D0:
D1:
TEN1
D2:
REN2/
D3:
TEN2
D4:
RX1
D5:
TX1
D6:
RX2
D7:
TX2
Note:
Any of these pins can be read by software. Therefore, unused func-
tions can be used as general purpose inputs, notably external enable
lines when the internal serial decoder is used.
Port R is an 8-bit bidirectional I/O port available for general
purpose I/O operations. Port R has a direction register to
enable each separate pin to be individually defined as an
input or output. It has a data register which contains the
value to be output. In addition, the Port R pins can be read
directly using the Port R pins address.
10
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| HPC-DEV-SYS2-E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController |
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| HPC-DEV-SYS4-E | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance microController with A/D |
| HPC-DEV-WDBC | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController |
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