參數(shù)資料
型號: HPC-DEV-SYS2
廠商: National Semiconductor Corporation
英文描述: High-Performance Communications MicroController
中文描述: 高性能通信微控制器
文件頁數(shù): 9/30頁
文件大?。?/td> 362K
代理商: HPC-DEV-SYS2
Timing Waveforms
(Continued)
Serial Decoder Timing Diagram (Modes 5, 6,7)
TL/DD/10422–16
Symbol
Parameter
Min
Max
Comments
Units
TPFS
TAFS
TEFS
TLFS
TVFC
THFS
TSFS
TTTC
Number of HCK1 Periods between FS Rising Edges
Number of HCK1 Falling Edges during FS High
Hold of FS Low after HCK1 Falling Edge
Setup of FS Rising Edge before HCK1 Falling Edge
Delay of TX Output Valid after HCK1 Rising Edge
Hold of FS High after HCK1 Falling Edge
Setup of FS Falling Edge before HCK1 Rising Edge
Delay of TX output TRI-STATE after HCK1 Rising Edge
34
1
10
45
32
Early FS
ns
ns
ns
ns
ns
ns
Late FS, (Note 8)
(Note 7)
60
20
20
40
Note 7:
This spec is for 1st bit only. Remaining bits are spec’d by transmitter TVTC spec.
Note 8:
Receiver specs TVRS and TVRH are required along with TLFS for receiver operation using serial decoder.
9
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